公开(公告)号：EP1573823A4

公开(公告)日：2009-03-25

申请号：EP03790326

申请日：2003-12-05

Applicant: IBM

Inventor： NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An MOS device with first and second freestanding semiconductor bodies (40N, 40P) formed on a substrate (10). The first freestanding semiconductor body (40N or 40P) has a first portion thereof disposed at a non-orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body (40P or 40N). These portions of said first and second freestanding semiconductor bodies (40N, 40P) have respective first and second crystalline orientations. A first gate electrode (60) crosses over at least part of said first portion of said first freestanding semiconductor body (40N or 40P) at a non-orthogonal angle, as does a second gate electrode (60) over the first portion of the second freestanding semiconductor body (40P or 40N).

公开(公告)号：EP1532659A4

公开(公告)日：2005-12-14

申请号：EP03736783

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

Abstract: The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：EP2281303A4

公开(公告)日：2013-11-20

申请号：EP09798429

申请日：2009-06-18

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/334 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

公开(公告)号：EP1805795A4

公开(公告)日：2010-10-06

申请号：EP05809789

申请日：2005-10-11

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

公开(公告)号：EP1787331A4

公开(公告)日：2010-09-29

申请号：EP05725829

申请日：2005-03-18

Applicant: IBM

Inventor： CLARK WILLIAM F JR ,  NOWAK EDWARD J

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/84 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818

公开(公告)号：EP1977446A4

公开(公告)日：2009-09-23

申请号：EP07710062

申请日：2007-01-11

Applicant: IBM

Inventor： ANDERSON BRENT A ,  CHAN VICTOR W C ,  NOWAK EDWARD J

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/76 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

公开(公告)号：EP1692724A4

公开(公告)日：2007-11-21

申请号：EP03796818

申请日：2003-12-08

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L27/148 ,  H01L21/336 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit semiconductor memory device (100) has a first dielectric layer (116) characterized as the BOX layer absent from a portion (130) of the substrate (112) under the gate of a storage transistor to increase the gate-to-substrate capacitance and thereby reduce the soft error rate. A second dielectric layer (132) having a property different from the first dielectric layer at least partly covers that portion (130) of the substrate. The device may be a FinFET device including a fin (122) and a gate dielectric layer (124, 126) between the gate and the fin, with the second dielectric layer having less leakage than the gate dielectric layer.

公开(公告)号：EP1644988A4

公开(公告)日：2007-04-11

申请号：EP04777137

申请日：2004-06-25

Applicant: IBM

Inventor： NOWAK EDWARD J

IPC: H01L27/108 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/786 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: The invention provides a method of manufacturing a fin-type field effect transistor (FinFET) that begins by patterning a rectangular loop of semiconductor material (16) having two longer fins (21) and two shorter sections (22). The longer fins (21) are perpendicular to the shorter sections (22). The process continues by patterning a rectangular gate conductor (20) over central sections of the two longer fins (21), wherein the gate conductor (20) is perpendicular to the two longer fins (21). Next, the invention dopes portions of the semiconductor material (11) not covered by the gate conductor (20) to form source and drain regions in portions of the fins (21) that extend beyond the gate (20). Following this, the invention forms insulating sidewalls (31) along the gate conductor (20). Then, the invention covers the gate conductor (20) and the semiconductor material (11) with a conductive contact material (30) and forms a contact mask (40) over a portion of the conductive contact material (30) that is above source and drain regions of a first fin (42) of the two longer fins (21). The invention follows this by selectively etching regions of the conductive contact material (30) and the semiconductor material (11) not protected by the contact mask. This leaves the conductive contact material (30) on source and drain regions of the first fin (42) and removes source and drain regions of a second fin (41) of the two longer fins (21). This process forms a unique FinFET that has a first fin (42) with a central channel region (55) and source and drain regions (56) adjacent the channel region (55), a gate (20) intersecting the first fin (42) and covering the channel region (55), and a second fin (41) having only a channel region. The second fin is parallel to the first fin (42) and covered by the gate.

公开(公告)号：EP2070110A4

公开(公告)日：2012-01-25

申请号：EP07842398

申请日：2007-09-13

Applicant: IBM

Inventor： ANDERSON BRENT A ,  LUDWIG THOMAS ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66613 ,  H01L29/66795 ,  H01L2029/7858

公开(公告)号：EP1920467A4

公开(公告)日：2011-03-02

申请号：EP06788172

申请日：2006-07-21

Applicant: IBM

Inventor： NOWAK EDWARD J

IPC: H01L27/108 ,  H01L21/336 ,  H01L29/06 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/66818 ,  H01L29/7856