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    HIGH PERFORMANCE INTEGRATED CIRCUIT CHIP PACKAGE AND METHOD OF MAKING SAME
    22.
    发明专利
    HIGH PERFORMANCE INTEGRATED CIRCUIT CHIP PACKAGE AND METHOD OF MAKING SAME 未知

    公开(公告)号：CA2002213C

    公开(公告)日：1999-03-30

    申请号：CA2002213

    申请日：1989-11-03

    Applicant: NORTHERN TELECOM LTD ,  IBM ,  MCNC

    Inventor： TURLIK IWONA ,  REISMAN ARNOLD ,  NAYAK DEEPAK ,  HWANG LIH-TYNG ,  DISHON GIORA ,  JACOBS SCOTT L ,  DARVEAUX ROBERT FRANCIS ,  POLEY NEIL M

    IPC: H01L23/373 ,  H01L23/473 ,  H01L23/538 ,  H01L25/065 ,  H01L23/34

    Abstract: A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The multilayer wiring substrate may be formed by a self-aligned thin film wiring method, with a self-aligned lift off method being employed to form internal wiring planes. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

    23.
    发明专利
    未知

    公开(公告)号：IT1151001B

    公开(公告)日：1986-12-17

    申请号：IT1961580

    申请日：1980-02-01

    Applicant: IBM

    Inventor： KUMAR RAY ASIT ,  REISMAN ARNOLD

    IPC: C23C8/36 ,  H01L21/31 ,  H01L21/316 ,  H01L

    Abstract: Uniform growth of oxide at low temperature can be performed in a plasma environment by positioning the substrates on which the oxide is to grow outside of the plasma area and independently supplying heat to the substrates in the presence of controlled oxygen pressure.

    METHOD OF FORMING SMOOTH AND PINHOLE-FREE SILICON CARBIDE FILMS ON A SILICON SUBSTRATE
    24.
    发明专利
    METHOD OF FORMING SMOOTH AND PINHOLE-FREE SILICON CARBIDE FILMS ON A SILICON SUBSTRATE 未知

    公开(公告)号：DE2862062D1

    公开(公告)日：1982-11-25

    申请号：DE2862062

    申请日：1978-07-20

    Applicant: IBM

    Inventor： BALOG MOSHE ,  BERKENBLIT MELVIN ,  CHAN SEE-ARK ,  REISMAN ARNOLD

    IPC: C30B25/02 ,  B41J2/16 ,  C04B41/50 ,  C04B41/87 ,  C23C16/32 ,  C30B29/06 ,  C30B29/36 ,  B41J3/04 ,  C01B31/36

    Abstract: The invention provides a method for forming a protective silicon carbide (SiC) film on a silicon (Si) substrate. The method permits the formation of silicon carbide on the Si substrate on all surfaces simultaneously. The process is highlighted in that the silicon substrate to be coated is placed in a susceptor having tantalum carbide surfaces and which has a high purity ambient. The substrate is heated at a temperature about 1250 DEG C to remove native SiO2 from its surface. The system is then cooled to a temperature of about 900 DEG C and methane is added for about 30 minutes to thereby deposit a layer of carbon which is further reacted with the Si substrate at 1250 DEG C to form a smooth, pin hole free SiC film. SiC layers are also formed by a one step reaction in which methane is reacted directly with Si at 1250 DEG C.

    26.
    发明专利
    未知

    公开(公告)号：DE2750505A1

    公开(公告)日：1978-06-22

    申请号：DE2750505

    申请日：1977-11-11

    Applicant: IBM

    Inventor： PARK KYU C ,  REISMAN ARNOLD

    IPC: H01J31/24 ,  G02B27/50 ,  H01J9/233 ,  H01J29/39 ,  H01J9/02 ,  H01J31/08

    Abstract: A process for the fabrication of a deformographic storage display tube (DSDT) target in which a wafer of silicon or other etchable material is used (1) as a temporary support during the generation of the active region of the target and (2) as a supporting structure for the completed target. The DSDT target structure comprises a reflection layer on a dielectric layer supported in turn on a silicon or other etchable material wafer, the wafer being etched off at its back side to expose the dielectric layer while providing an outer frame support structure made of the wafer around the edge, with the dielectric layer being etched to form pillars of the dielectric on the backside of the reflection layer, whereby the dielectric pillars enable a deformation action to occur in the region between the pillars. An inner frame support structure comprised of a similarly etched wafer, a dielectric layer and a secondary electron emission layer is fitted against the bottoms of the pillars and bonded to the outer frame support structure, thereby forming the completed target.

    GLASS MAKING PROCESS
    28.
    发明专利
    GLASS MAKING PROCESS 未知

    公开(公告)号：AU6751774A

    公开(公告)日：1975-10-09

    申请号：AU6751774

    申请日：1974-04-03

    Applicant: IBM

    Inventor： LUSSOW ROBERT OTIS ,  REISMAN ARNOLD ,  BERKENBLIT MELVIN

    IPC: C03C27/04 ,  C03B19/00 ,  C03C3/072 ,  C03C3/102 ,  C03C17/02 ,  C03C27/06 ,  C03C27/10 ,  C03C3/30

    Abstract: A process for the in situ fabrication of a glass from an admixed frit, for example, of two starting glasses on the required existing substrate structure therefore. The admixed frit comprises a low glass transition temperature glass and a higher glass transition temperature glass, which glasses are uniquely capable of forming a continuous vitreous phase over their entire compositional range. During thermal cycling, the low glass transition temperature glass flows out and solubilizes the higher glass transition temperature glass to thereby synthesize in situ a new glass. The temperature required to form the glass by the in situ process is less than that required where a glass of identical composition is first preequilibrated externally and then applied in frit form to the existing substrate structure and flowed out thereon. The in situ synthesized new glass softens and flows at a temperature higher than that of the low glass transistion temperature glass and lower than that of the higher glass transition temperature glass, and exhibits a glass transition temperature intermediate to the two starting glasses.

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