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    21.
    发明专利
    未知

    公开(公告)号：DE2337159A1

    公开(公告)日：1975-02-13

    申请号：DE2337159

    申请日：1973-07-21

    Applicant: IBM DEUTSCHLAND

    Inventor： DRESCHER HEINZ ,  RUDOLPH PETER ,  LAMPE HANS HERMANN ,  POHLE WERNER ,  DOEHLE LOTHAR

    IPC: G06F9/48 ,  G06F13/18 ,  G06F13/366 ,  G06F9/18

    Abstract: A priority control circuit for establishing connections between a data handling system element and a number of subsystems wherein request signals from subsystems are scanned and granted service in a sequence which is determined by their position in a priority ranking order. The scanner returns to the beginning of the order immediately after a request has been granted, the subsystem just serviced being bypassed in the next scan until all of the remaining request signals have been processed. Each time a request signal is encountered and service granted, the scanner returns to the beginning of the order, a new scan is begun and all prior requests serviced are bypassed. In the absence of any other requests or after all of the request signals have been serviced the bypassed subsystems are unlocked and a scan of all requests is begun.

    25.
    发明专利
    未知

    公开(公告)号：DE3886529D1

    公开(公告)日：1994-02-03

    申请号：DE3886529

    申请日：1988-08-27

    Applicant: IBM

    Inventor： RUDOLPH PETER ,  BOCK DIETRICH W DIPL ING ,  SCHULZE-SCHOELLING HERMANN ING ,  MANNHERZ PETER DIPL ING

    IPC: G01R31/3185 ,  G06F1/24 ,  G06F11/14 ,  G06F1/00 ,  G06F11/00

    Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation (e.g.processing/logging error data) prior to a processor start. One or more reset areas are defined which are initialized /reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause (e.g. power-on) for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

    28.
    发明专利
    未知

    公开(公告)号：DE2355994A1

    公开(公告)日：1975-07-03

    申请号：DE2355994

    申请日：1973-11-09

    Applicant: IBM DEUTSCHLAND

    Inventor： LAMPE HANS HERMANN ,  RUDOLPH PETER ,  HAHN GUENTER

    IPC: G01R13/00 ,  G01R13/40 ,  G01R13/04

    Abstract: An arrangement for the dynamic direct display of pulses in the nanosecond range operates without oscilloscopes or other special display apparatus. To display pulse timing or amplitude characteristics, a pulse sequence is applied to an equidistant tapped delay line, the output from each tap being connected to a bistable storage element with an indicator lamp in the output. A plurality of indicator lamps are arranged in the form of a matrix. If a pulse occurs on a tap during a sampling interval, the associated indicator lamp is turned on. The sequence and identity of the turned on indicators is indicative of the pulse spacing and the pulse width in the pulse sequence.

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