-
公开(公告)号:JPH0551175B2
公开(公告)日:1993-07-30
申请号:JP200587
申请日:1987-01-09
Applicant: IBM
Inventor: KARANAMU BARASABURAMANYAMU , ANSONII JON DARI , YAKOBU RAIZUMAN , SEIKI OGURA
IPC: H01L21/3205 , G03F7/09 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L21/90
-
公开(公告)号:JPH0541487A
公开(公告)日:1993-02-19
申请号:JP4372191
申请日:1991-03-08
Applicant: IBM
Inventor: DOMINIKU BONUU , MIRIAMU KOMUBE , ANSONII JIEI DARII , PIEERU MORIE , SEIKI OGURA , PASUKARU TANOFU
IPC: H01L27/06 , H01L21/331 , H01L21/8249 , H01L29/08 , H01L29/73 , H01L29/732 , H01L29/74
Abstract: PURPOSE: To provide a high-performance longitudinal-type insulating collector PNP transistor structure. CONSTITUTION: This structure includes a P -region 45 for emitter, N-region 44 for base and P-well region 46 for collector, the P-well region 46 is surrounded with an N-type pocket composed of an N -embedded layer 48 and an N reach- through area 47 in contact with this layer 48, contact regions 46-1 and 47-1 in the P-well region 46 and the N reach-through region 47 are short-circuitted, and a common metal contact 59 is formed. A thickness W in the P-well region 46 is suppressed to a minimum, so as to allow the transistor operation of parasitic NPN transistor formed from the N region 44, P-well region 46 and N - embedded layer 48. PNPN thyristor structure is formed, so as to make this parasitic PNP transistor parallel with the PNP transistor and problems caused by increase in the collector resistance of P-well region are canceled.
-
公开(公告)号:JPH0323673A
公开(公告)日:1991-01-31
申请号:JP14754790
申请日:1990-06-07
Applicant: IBM
Inventor: KURISUTOFUAA FURANKU KOODERA , NIBO ROBUEDO , SEIKI OGURA
IPC: H01L21/28 , H01L21/336 , H01L29/10 , H01L29/78
Abstract: PURPOSE: To make the dynamic characteristic good by providing source and drain regions of a second conductivity type separated by channel regions on the surface of a semiconductor substrate of a first conductivity type, coupling drain extensions of a lower dopant concn. than that of the drain region with channels and providing gate electrodes thereon. CONSTITUTION: An N type source region 14 and N type drain region 16 of an IGFET 10 are formed while separating them by a channel portion 18. On a channel part 18, a gate structure 20 is formed, including a doped polycrystal, Al-Cu electrodes 22 covered with Si3 N4 side walls 26A, 26B at both sides through an SiO2 thin film 24. A lightly doped N type region 30 is added to the lower face of the source region 14, the ends are coupled with one end of the channel part 18, and N type region 28 on the top end of the drain region 16 is coupled with the other end of the channel region 18. This allows the gate length to be on the order of submicrons and makes the dynamic characteristic good.
-
公开(公告)号:JPH02215158A
公开(公告)日:1990-08-28
申请号:JP32860589
申请日:1989-12-20
Applicant: IBM
Inventor: SEIKI OGURA , NIBO ROBEDO
IPC: H01L29/73 , H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/07
Abstract: PURPOSE: To obtain a common manufacturing method which unifies the manufacture of a bipolar device and a CMOS device by using a prescribed treatment stage. CONSTITUTION: The structure of a Bi-CMOS device is designed so that its bipolar parts and CMOS parts can share the same structural feature. In the treatment stage of the device, the gate oxide of an emitter is removed while the gate oxide of an FFT is maintained by forming a reach-through N subcollector to a bipolar device without performing any excessive process and one mask by combining a threshold adjusting/well implant with self-aligned insulation leakage protective implant by using a self-aligned removable oxide mask before separating a field and protecting the emitter and base from being punched through while the base is aligned with a pedestal in a self-aligning way.
-
公开(公告)号:JPS62235758A
公开(公告)日:1987-10-15
申请号:JP200587
申请日:1987-01-09
Applicant: IBM
Inventor: KARANAMU BARASABURAMANYAMU , ANSONII JIYON DARI , YAKOBU RAIZUMAN , SEIKI OGURA
IPC: H01L21/3205 , G03F7/09 , H01L21/027 , H01L21/302 , H01L21/3065 , H01L21/768
-
-
-
-