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    DRAM
    23.
    发明专利
    DRAM 失效

    公开(公告)号：JP2002298577A

    公开(公告)日：2002-10-11

    申请号：JP2001097915

    申请日：2001-03-30

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO

    IPC: G11C7/18 ,  G11C11/406 ,  G11C11/4097

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM in which power consumption of refreshing is reduced to degree of a data retention mode of a low/medium speed SRAM. SOLUTION: This device has such constitution that the number of word lines intersecting with bit lines is made 1/n (n: positive integer) of the prescribed number of lines with making the number of word lines for each block 12a into the prescribed number of lines and making the number of blocks 12a (n) times. Length of bit lines is shortened, capacity of bit lines is reduced, and power consumption of a memory array 16a is reduced.

    MEMORY SYSTEM AND DATA TRANSFER METHOD
    24.
    发明专利
    MEMORY SYSTEM AND DATA TRANSFER METHOD 失效

    公开(公告)号：JPH10111828A

    公开(公告)日：1998-04-28

    申请号：JP25712796

    申请日：1996-09-27

    Applicant: IBM

    Inventor： WATANABE SHINPEI ,  SUNANAGA TOSHIO

    IPC: G06F12/00 ,  G11C7/10 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4096

    Abstract: PROBLEM TO BE SOLVED: To provide a memory system which is constituted of DRAM capable of executing seamless operation by not only a reading operation but also a writing operation by preventing band width from being substantially reduced as compared with a clock pulse frequency regardless of in which bank access is performed and in which order it is executed. SOLUTION: Memory array is separated from data in an early stage by applying pre-fetch mechanism in reading and writing so as to prevent the energizing and pre-fetching operations, etc., which are the ones required for succeeding reading in memory array from being the main cause of reduction in access speed. Two-fold data of an array time constant is pre-fetched so that the both of reading ans writing are simultaneously realized concerning the seamless operation by singlel bank configuration in spite of any kind of low-access.

    SENSE CIRCUIT FOR SEMICONDUCTOR MEMORY, WHOSE VOLTAGE SWING OF BIT LINE IS LIMITED
    25.
    发明专利
    SENSE CIRCUIT FOR SEMICONDUCTOR MEMORY, WHOSE VOLTAGE SWING OF BIT LINE IS LIMITED 失效

    公开(公告)号：JPH0684358A

    公开(公告)日：1994-03-25

    申请号：JP560493

    申请日：1993-01-18

    Applicant: IBM

    Inventor： SAN HOO DON ,  KITAMURA TSUNEJI ,  KIRIHATA TOSHIAKI ,  SUNANAGA TOSHIO

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/407 ,  G11C11/4091

    Abstract: PURPOSE: To reduce the swing of a bit line by limiting the swing of a rise bit line to prescribed voltage higher than power voltage. CONSTITUTION: External voltages VCC and VSS are used for a word line driver 20, PMOS cell array 16 in an n-type well, a COMS AC connection sense amplifier 18 and a bit line monitor circuit 22. Since an initial bit line is precharged by VEQ which is larger than the threshold of QPCELL of VTP, a signal can be generated at high speed. A signal charge appearing on the bit line BL30 from an access cell is speedily detected in the sense amplifier at sense clocks ϕSR and ϕSP. Here, voltages VCC and VSS charge rise BL and discharge fall BL. Thus, sense speed improves. At that time, a reference bit is monitored in the monitor circuit 22, non-activates clocks ϕ1 and ϕ2 and limits voltage when it reaches setting voltage. Then, the swing of boosting voltage is limited between a power source and setting voltage and the swing of the bit line can be reduced.

    Semiconductor memory device
    26.
    发明专利
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：JP2007128610A

    公开(公告)日：2007-05-24

    申请号：JP2005320982

    申请日：2005-11-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： SUNANAGA TOSHIO

    IPC: G11C11/401

    CPC classification number: G11C8/10 ,  G11C7/08 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which active current is reduced by reducing the number of sense amplifiers to be simultaneously activated.
    SOLUTION: This SDRAM has a divided word line structure, and includes a plurality of banks. Each bank BNK0 includes arrays AR1 to 64 and a main word line MWL of 4K. A row address signal is captured according to a row address strobe signal, and a segment address signal is captured according to a column address strobe signal. A main row decoder MRD simultaneously activates main word lines MWL1, 5, 9 and 13 according to the row address signal. The segment row decoder SRD selects only the array AR1 according to the segment address signal, and activates only a sense amplifier SA of 1K corresponding to the selected array AR1. The main word lines MWL1, 5, 9 and 13 are activated, however the segment word lines of the arrays 2 to 64 are not activated, and no data is therefore destroyed.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种通过减少要同时激活的读出放大器的数量来降低有功电流的半导体存储器件。 解决方案：该SDRAM具有划分的字线结构，并且包括多个存储体。 每个银行BNK0包括阵列AR1至64和主字线MWL为4K。 根据行地址选通信号捕获行地址信号，根据列地址选通信号捕获段地址信号。 主行解码器MRD根据行地址信号同时激活主字线MWL1,5,9和13。 分段行解码器SRD根据段地址信号仅选择阵列AR1，并且仅激活与所选阵列AR1相对应的1K的读出放大器SA。 主字线MWL1,5,9和13被激活，但阵列2至64的段字线未被激活，因此不会破坏数据。 版权所有（C）2007，JPO＆INPIT

    Semiconductor storage device
    27.
    发明专利
    Semiconductor storage device 有权
    半导体存储设备

    公开(公告)号：JP2007122817A

    公开(公告)日：2007-05-17

    申请号：JP2005314601

    申请日：2005-10-28

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： SUNANAGA TOSHIO

    IPC: G11C29/04 ,  G11C11/401

    CPC classification number: G11C11/408 ,  G11C29/806

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM in which consumption current is reduced in an address comparison circuit for comparing an address signal with a programmed defect address signal.
    SOLUTION: Arranging a redundant predecoder 56 for predecoding a defective row address signal DRA outputted from a program circuit 24, an address comparison circuit 54 compares a predecoding signal PRA, outputted from a predecoder 18, with a defective predecoding signal PDRA outputted from the redundant predecoder 56. In a 2-bit predecoding system, the address comparison circuit 54 compares 4 bits of the defective predecoding signal PDRA with the 4 bits of the predecoding signal PRA, respectively, and collectively compares a row address signal RA with the defective row address signal DRA in a batch of the 2 bits.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种在地址比较电路中消耗电流减小的DRAM，用于将地址信号与编程的缺陷地址信号进行比较。 解决方案：布置用于对编程电路24输出的有缺陷的行地址信号DRA进行预编码的冗余预解码器56，地址比较电路54将从预解码器18输出的预解码信号PRA与从预解码器18输出的故障预解码信号PDRA进行比较 冗余预解码器56.在2比特预解码系统中，地址比较电路54分别比较4个比特的缺陷预解码信号PDRA与预解码信号PRA的4比特，并将行地址信号RA与有缺陷的预解码信号 行地址信号DRA以2位的批次。 版权所有（C）2007，JPO＆INPIT

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