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公开(公告)号：JP2002100127A
公开(公告)日：2002-04-05
申请号：JP2001206336
申请日：2001-07-06
Applicant: IBM
Inventor： MARTIN OLERIANO HASUN , RICHARD MICHAEL H NE , ARUBINDO MOTEIBUHAI PEITO , TAMURA TETSUYA , BARRY MARSHALL TOREIJI
Abstract: PROBLEM TO BE SOLVED: To provide a decoding method and system which lessen the complicatedness of a maximum likelihood decoding method and the waiting time for results without significantly affecting performance and without losing bit reliability information. SOLUTION: A software error correction algebra decoder and an associated method derive an error position and value by using the degrees of erasure reliability. More specifically, the degrees of the signal reliability from the maximum likelihood(ML) decoder and the parity check success/failure from an internal modulation code symbol are iteratively combined in such a manner that an error erasure rate is maximized. The software error correction (ECC) algebra decoder and the associated method decode a Reed-Solomon code by using the information on the binary code and detector side. The Reed-Solomon code is optimized for the purpose of use on an erasure channel. A threshold regulation algorithm modifies an erasure candidate in accordance with the detector error filter output and modulation code restriction success/failure information.
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公开(公告)号：JP2000206879A
公开(公告)日：2000-07-28
申请号：JP738499
申请日：1999-01-14
Applicant: IBM
Inventor： TAMURA TETSUYA
Abstract: PROBLEM TO BE SOLVED: To realize a group calculation on a Jacobi variety by a small amount of operations. SOLUTION: This device for operating group calculations to the factors of a Jacobi variety of a hyperelliptic curve y2+y=f(x) defined on GF(2n)D1=g.c. d. (a1(x), y-b1(x)) and D2=g.c.d.(a2(x), y-b2(x)) has a means for storing a1(x), a2(x), b1(x), and b2(x), and a means for calculating q(x)= s1(b1(x)+b2(x))) mod a2(x) by using s1(x) satisfying s1(x) a1(x)+s2(x)a2(x)=1 in the case of GCD(a1(x), a2(x))=1 (GCD is a greatest common polynomial). Thus, the calculations are decreased in the amount by arranging the new function q(x), and can also be operated by a reduced quantity of hardware. Moreover, in the case of D1=D2, this device is provided with a means for storing a1(x) and b1(x), and a means for calculating q(x)=Q(b12(x)+f(x) mod a12(x), a1) Q(A, B) is a quotient of A divided by B}.
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Patent Agency Ranking
公开(公告)号：JPH0962760A
公开(公告)日：1997-03-07
申请号：JP21033995
申请日：1995-08-18
Applicant: IBM
Inventor： TAMURA TETSUYA , TERUKINA ASAO , NOZAWA TORU , KOYAMA SEIJI , MAATEIN HASUNAA
Abstract: PROBLEM TO BE SOLVED: To output the same integration result for the same bit pattern even if the variation of an integrating period, a semiconductor process and power source voltage, etc., exists. SOLUTION: This integrator is provided with a first integrator 1 having a first amplifier 1 and integrating reference voltage during an integrating period, a second integrator having a second amplifier 11 and integrating an input signal during the integrating period and a control means 7 outputting the signal adjusting the gain of the first amplifier 1 to the first amplifier 1 and adjusting the gain of the second amplifier 11 by using the signal adjusting this gain, so that the output of the first integrator may be changed according to the integrating period.
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公开(公告)号：MY134625A
公开(公告)日：2007-12-31
申请号：MYPI20034023
申请日：2003-10-22
Applicant: IBM
Inventor： ASANO HIDEO , HASSNER MARTIN AURELIANO , HEISE NYLES NORBERT , HETZLER STEVEN R , TAMURA TETSUYA
IPC: G06F11/10 , G11B5/09 , G06F11/00 , G11B20/18 , H03M13/00 , H03M13/03 , H03M13/11 , H03M13/15 , H03M13/29 , H03M13/47
Abstract: AN ENCODING SYSTEM AND ASSOCIATED METHOD PROTECT AGAINST MISCORRECTION DUE TO PARITY SECTOR CORRECTION IN, FOR EXAMPLE, AN ON-DRIVE RAID SYSTEM. THE SYSTEM ADDS A PARITY CLUSTER BLOCK, WHICH ITSELF IS A COMPLETE, C3-PROTECTED CLUSTER. HAVING THE CLUSTER LEVEL, C4 LEVEL CORRECTION, BY PARITY SECTORS, CHECKED AND VERIFIED BY C3 CHECKS THAT HAVE HIGH RELIABILITY LEVEL, AS WELL AS THE CAPABILITY FOR CHECKING CONSISTENCY OF A CLUSTER BLOCK, EVEN IN THE PRESENCE OF "JAMI" ERRORS, MAKES THIS POSSIBILITY UNLIKELY. A SCRUB ALGORITHM AVOIDS READ-MODIFY-WRITE OPERATIONS BY DEFERRING THE COMPLETION OF THE C2 AND C3-CKECKS UNTIL THE STORAGE DEVICE IS ADLE.(FIG 5)
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公开(公告)号：DE69614772D1
公开(公告)日：2001-10-04
申请号：DE69614772
申请日：1996-06-10
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , TAMURA TETSUYA , WINOGRAD SHMUEL
Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.
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公开(公告)号：ES2145100T3
公开(公告)日：2000-07-01
申请号：ES94304678
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：AT192614T
公开(公告)日：2000-05-15
申请号：AT94304678
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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