公开(公告)号：MY141640A

公开(公告)日：2010-05-31

申请号：MYPI9706319

申请日：1997-12-26

Applicant: IBM

Inventor： FEILCHENFELD NATALIE BARBARA ,  KRESGE JOHN STEVEN ,  MOORE SCOTT PRESTON ,  NOWAK RONALD PETER ,  WILSON JAMES WARREN

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/60 ,  H01L23/04 ,  H01L23/12 ,  H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H05K1/05 ,  H05K3/40 ,  H05K3/46

Abstract: THE PRESENT INVENTION PROVIDES AN ORGANIC CHIP CARRIER (10) PARTICULARLY USEFUL WITH FLIP CHIPS (42), COMPRISING AN ORGANIC DIELECTRIC LAYER (22), A FIRST LAYER OF CIRCUITRY (25) DISPOSED ON THE DIELECTRIC LAYER, AN ORGANIC CONFORMATIONAL COATING (34) DISPOSED OVER THE FIRST LAYER OF DIELECTRIC AND THE FIRST LAYER OF CIRCUITRY, AND A LAYER OF FINE LINE CIRCUITRY (40) HAVING LINE WIDTH OF ABOUT 0. 0508 MM (2.0 MIL) OR LESS. PREFERABLY ABOUT 0.0254 MM (1.0 MIL) OR LESS, PREFERABLY ABOUT 0.01778 MM (0.7 MIL), AND A SPACE BETWEEN LINES OF ABOUT 0.0381 MM (1.5 MIL) OR LESS, PREFERABLY ABOUT 0.02794 MM (1.1 MIL) OR LESS, DISPOSED ON THE CONFORMATIONAL LAYER. PREFERABLY THE DIELECTRIC LAYER IS FREE OF WOVEN FIBER GLASS. THE CONFORMATIONAL COATING PREFERABLY HAS A DIELECTRIC CONSTANT OF ABOUT 1.5 TO ABOUT 3.5, AND A PERCENT PLANARIZATION OF GREATER THAN ABOUT 3.5%. THE INVENTION ALSO RELATES TO METHODS OF MAKING THE DIELECTRIC COATED CHIP CARRIER.

公开(公告)号：DE69615930D1

公开(公告)日：2001-11-22

申请号：DE69615930

申请日：1996-05-17

Applicant: IBM

Inventor： WILSON JAMES WARREN ,  ENGLE STEPHEN ROBERT ,  MOORE SCOTT PRESTON

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/13 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498

Abstract: Thermally enhanced electronic package (30) has a first electronic component (32) and a number of discrete connectors (36) bonded to a thermally conductive member (34) having a first coefficient of thermal expansion. The connectors have at least one coefficient of thermal expansion different from the first and have fusible conductors (38) on at least one surface and conductive passageways, the electronic component being electrically connected to the passageways in the members and via them to the fusible conductors.

公开(公告)号：SG54966A1

公开(公告)日：1998-12-21

申请号：SG1995000495

申请日：1995-05-23

Applicant: IBM

Inventor： WILSON JAMES WARREN

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373 ,  H05K1/02 ,  H05K3/28 ,  H05K3/42 ,  H01L23/15 ,  H01L23/498

Abstract: A semiconductor chip package and method of making same wherein the package comprises a ceramic substrate having two layers of thermally and electrically conductive material (e.g., copper) on opposing surfaces thereof, these layers thermally and electrically coupled by metal material located within holes provided in the ceramic. A semiconductor chip is mounted on one of these layers and the contact sites thereof electrically coupled to spaced circuitry which, in a preferred embodiment, is formed simultaneously with both thermally conductive layers. Coupling of the circuitry to an external substrate (e.g., printed circuit board) is preferably accomplished using metallic spring clips. These clips are preferably soldered in position. A preferred metal for being positioned within the hole(s) is solder, one example being 10:90 tin:lead solder. The package as produced herein may further include two quantities of a protective encapsulant material located substantially on the upper portions thereof to protect the chip and circuitry. The preferred means for coupling the chip to the circuitry is to use a wire bonding operation.

公开(公告)号：PL324177A1

公开(公告)日：1998-07-20

申请号：PL32417798

申请日：1998-01-08

Applicant: IBM

Inventor： MACQUARRIE STEPHEN WESLEY ,  STORR WAYNE RUSSELL ,  WILSON JAMES WARREN

IPC: H01L21/60 ,  H01L21/58 ,  H01L21/70 ,  H01L23/00 ,  H01L23/053 ,  H01L23/12 ,  H01L23/14 ,  H01L23/28 ,  H01L23/32 ,  H01L23/36 ,  H01L23/495 ,  H01L27/00 ,  H01L27/12

Abstract: A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)

公开(公告)号：HU9701377D0

公开(公告)日：1997-10-28

申请号：HU9701377

申请日：1997-08-11

Applicant: IBM

Inventor： MACQUARRIE STEPHEN WESLEY ,  STORR WAYNE RUSSEL ,  WILSON JAMES WARREN

IPC: H01L21/60 ,  H01L21/58 ,  H01L21/70 ,  H01L23/00 ,  H01L23/053 ,  H01L23/12 ,  H01L23/14 ,  H01L23/28 ,  H01L23/32 ,  H01L23/36 ,  H01L23/495 ,  H01L27/00 ,  H01L27/12

Abstract: A PACKAGE FOR MOUNTING AN INTEGRATED CIRCUIT CHIP (30, 52) TO A CIRCUIT BOARD (48) OR THE LIKE IS PROVIDED. THE PACKAGE INCLUDES A CHIP CARRIER (10) WHICH HAS A METAL SUBSTRATE (12) INCLUDING FIRST AND SECOND OPPOSED FACES. A DIELECTRIC COATING (20) IS PROVIDED ON AT LEAST ONE OF THE FACES, WHICH PREFERABLY IS LESS THAN ABOUT 20 MICRONS IN THICKNESS, AND PREFERABLY HAS A DIELECTRIC CONSTANT FROM ABOUT 35 TO ABOUT 4.0. ELECTRICAL CIRCUITRY IS DISPOSED ON THE DIELECTRIC COATING, SAID CIRCUITRY INCLUDING CHIP MOUNTING PADS (22), CONNECTION PADS (24) AND CIRCUIT TRACES (26) CONNECTING THE CHIP MOUNTING PADS TO THE CONNECTION PADS. AN IC CHIP IS MOUNTED BY FLIP CHIP OR WIRE BONDING OR ADHESIVE CONNECTION ON THE FACE OF THE METAL SUBSTRATE WHICH HAS THE DIELECTRIC COATING THEREON. IN ANY CASE, THE IC CHIP IS ELECTRICALLY CONNECTED TO THE CHIP MOUNTING PADS EITHER BY THE SOLDER BALL (54) OR WIRE BOND (36) CONNECTIONS. ELECTRICAL LEADS (38, 60) EXTEND FROM THE CONNECTION PADS ON THE CHIP CARRIER AND ARE CONNECTED TO CORRESPONDING PADS ON A CIRCUIT BOARD OR THE LIKE TO PROVIDE I/O SIGNALS FOR THE IC CHIP. IN CERTAIN EMBODIMENTS, ADDITIONAL HEAT SINKS (62) CAN BE ATTACHED TO THE CHIP CARRIER AND, ALSO IN CERTAIN EMBODIMENTS, CHIPS CAN BE MOUNTED ON BOTH SIDES OF THE CHIP CARRIER TO INCREASE THE CAPACITY OF THE CHIP CARRIER. (FIG. 1)

公开(公告)号：CA2126121C

公开(公告)日：1997-09-16

申请号：CA2126121

申请日：1994-06-17

Applicant: IBM

Inventor： CHASE ALAN WALTER ,  WILSON JAMES WARREN

IPC: C08L75/04 ,  C08L75/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/12

Abstract: A chip carrier is disclosed which includes a chip carrier substrate and at least one semiconductor chip mounted in a flip chip configuration, via solder balls, on a circuitized surface of the chip carrier substrate. The solder balls are encapsulated in a first encapsulant having a composition which includes an epoxy. In addition, at least a portion of the circuitry on the circuitized surface is encapsulated in a second encapsulant having a composition which includes a urethane, and which composition is chosen so that the second encapsulant exhibits a modulus of elasticity which is equal to or less than about 10,000 psi. As a consequence, the second encapsulant exhibits neither internal cracks, nor interfacial cracks at the interface with the first encapsulant, nor does the second encapsulant delaminate from the circuitized surface, when the chip carrier is thermally cycled.