公开(公告)号：DE10041375B4

公开(公告)日：2005-06-02

申请号：DE10041375

申请日：2000-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  MUELLER GERHARD ,  GOGL DIETMAR ,  KANDOLF HELMUT

IPC: G11C11/15 ,  G11C17/16 ,  G11C29/00

公开(公告)号：DE10121182C1

公开(公告)日：2002-10-17

申请号：DE10121182

申请日：2001-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAMMERS STEFAN ,  GOGL DIETMAR ,  MUELLER GERHARD

IPC: G11C29/00 ,  G11C11/00

Abstract: The memory has a number of planes (1,2,3) having magnetoresistive memory cell fields combined in the form of a cross point array or transistor array, with redundant magnetoresistive memory cell fields (20) provided on the same chip and distributed above the individual planes of the memory matrix, or provided by one of the planes of the memory array, allowing defective memory cells in one plane to be replaced by redundant memory cells of a different plane.

公开(公告)号：DE10051173C2

公开(公告)日：2002-09-12

申请号：DE10051173

申请日：2000-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C11/15

公开(公告)号：DE102005053717A1

公开(公告)日：2006-07-06

申请号：DE102005053717

申请日：2005-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/06

Abstract: A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.

公开(公告)号：AU2003293828A1

公开(公告)日：2004-07-09

申请号：AU2003293828

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE10112281A1

公开(公告)日：2002-09-26

申请号：DE10112281

申请日：2001-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/06

Abstract: A memory sense amplifier (10) for a semiconductor memory device (1) is provided with a compensation current source device (30) which generates a compensation current (Icomp) and feeds it to an interconnected bit line (4). Said compensation current (Icomp) is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device (20) on the selected and interlinked bit line device (4) that is substantially constant over time.

公开(公告)号：DE10038925A1

公开(公告)日：2002-03-14

申请号：DE10038925

申请日：2000-08-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  ROEHR THOMAS ,  BOEHM THOMAS

IPC: G11C11/14 ,  G11C8/08 ,  G11C8/10 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: An electronic driver connection for a memory matrix wordlines comprises a driver source (2) having many coded outputs (IV0 - IV3, V0). Many wordline switches (N1-16, P1-8) are controllable by a control signal (SLNP;SLN1;SLN2) and switchably connect the drive source output to the word lines. Independent claims are also included for the following: (a) a memory device according to the above; and (b) a nonvolatile magnetic semiconductor memory for the above.

公开(公告)号：DE50110011D1

公开(公告)日：2006-07-20

申请号：DE50110011

申请日：2001-07-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  ROEHR THOMAS DR ,  GOGL DIETMAR

IPC: G11C8/08 ,  G11C11/14 ,  G11C8/10 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: An electronic driver connection for a memory matrix wordlines comprises a driver source (2) having many coded outputs (IV0 - IV3, V0). Many wordline switches (N1-16, P1-8) are controllable by a control signal (SLNP;SLN1;SLN2) and switchably connect the drive source output to the word lines. Independent claims are also included for the following: (a) a memory device according to the above; and (b) a nonvolatile magnetic semiconductor memory for the above.

公开(公告)号：DE102005055436A1

公开(公告)日：2006-06-01

申请号：DE102005055436

申请日：2005-11-21

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC CORBEI

Inventor： BRAUN DANIEL ,  GOGL DIETMAR

IPC: H01L27/22 ,  G11C11/15

Abstract: The chip has a set of magnetoresistive memory cells each including a magnetic tunnel junction having fixed and free magnetic regions. The free magnetic region includes two ferromagnetic layers that are antiferromagnetically coupled, where a coil surrounds the memory chip for creating a magnetic offset field. The regions are stacked in a parallel, overlying relationship separated by a layer of non-magnetic material. An independent claim is also included for a method of writing to a random access memory.

公开(公告)号：DE10118196A1

公开(公告)日：2002-10-24

申请号：DE10118196

申请日：2001-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  GOGL DIETMAR

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: The method involves subjecting the TMR memory cell (TMR) to a transient reversible magnetic change while reading an information item by applying a current pulse and comparing the resulting changed current signal with the original current signal. The information is stored in the soft magnetic layer of the TMR cell. The pulse is applied to the write line.