公开(公告)号：DE10258199A1

公开(公告)日：2004-07-15

申请号：DE10258199

申请日：2002-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STOCKEN CHRISTIAN ,  PROELL MANFRED ,  DOBLER MANFRED ,  RESCH GERALD

IPC: G11C29/02 ,  G11C29/00

Abstract: A circuit arrangement can have a number of integrated circuit components, which are arranged on a carrier substrate. A reception circuit for receiving a control signal can be coupled to one of the connection pads on the input side and can be connected to each of the circuit components on the output side. A bridging circuit controlled by a test mode signal can electrically bridge the reception circuit. In a testing method, a plurality of connection pads can be connected to a first potential and at least one of the connection pads can be connected to a second potential. The bridging circuit can be activated and the current measured, by a test arrangement, at the at least one of the connection pads. Inspection for leakage currents in connections between input-side reception circuits and the circuit components can be measured.

公开(公告)号：DE10208737A1

公开(公告)日：2003-09-18

申请号：DE10208737

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUBER THOMAS ,  DOBLER MANFRED

IPC: G06F1/18 ,  G11C5/00 ,  H05K1/11 ,  H05K1/14 ,  G11C5/04

Abstract: An adapter apparatus for receiving memory modules, each of which has a plurality of data terminals and a plurality of control terminals, comprises first data terminals, first control terminals, a first socket for receiving a first memory module with second data terminals and second control terminals, wherein the second data terminals are associated to the data terminals of the first memory module, wherein the second control terminals are associated to the control terminals of the first memory module, a second socket for receiving a second memory module with third data terminals and third control terminals, wherein the third data terminals are associated to the data terminals of the second memory module, wherein the third control terminals are associated to the control terminals of the second memory module, a signal transformation circuit with an input and an output, wherein the input is connected to the first control terminals, and wherein the output is connected to the second control terminals and to the third control terminals, and wherein a second group of first data terminals is connected to the third data terminals.

公开(公告)号：DE10131007A1

公开(公告)日：2003-01-23

申请号：DE10131007

申请日：2001-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEGMEIER PETER ,  MARX THILO ,  DOBLER MANFRED

IPC: G11C11/408 ,  G11C11/409

Abstract: A device for driving a memory cell ( 601 ) of a memory module which can be operated with an external voltage (V EXT ) and an operating frequency (f CLK ), whereas the memory cell ( 601 ) has a capacitance ( 600 ) for storing charges and a transistor ( 602 ) for reading charges from the capacitance ( 600 ) and for writing charges to the capacitance ( 600 ), which transistor can be controlled with a control voltage (V PP ), which has a charge store ( 614 ) for supplying a control voltage (V PP ) which is greater than the external voltage (V EXT ). The charge store ( 614 ) being able to be charged by the external voltage (V EXT ), and the charging of the charge store ( 614 ) is able to be controlled by a charging control frequency (f CC ) derived from the operating frequency (f CLK ) of the memory module.

公开(公告)号：DE10130785A1

公开(公告)日：2003-01-23

申请号：DE10130785

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOBLER MANFRED ,  FINTEIS THOMAS

IPC: G11C29/18 ,  G11C29/00

Abstract: A memory module (100) operates in a normal mode and in a test mode (TM) and includes a device (102) for outputting data from the memory module (100) and a device (104) for isolating the device (102) for outputting of data, when the test mode (TM) is activated. A data masking device is provided for the isolating device (104) for specifically outputting only certain sections of the data when a data masking state (DQM) is activated Independent claims are given for the following: (A) A test device; and (B) A method for testing a memory module.

公开(公告)号：DE10104575A1

公开(公告)日：2002-08-29

申请号：DE10104575

申请日：2001-02-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DOBLER MANFRED ,  MAYER PETER ,  RETTENBERGER ARMIN ,  DONHAUSER JUERGEN ,  SCHELLINGER ANDREAS

IPC: G11C29/50 ,  G11C29/00

Abstract: The method involves measuring and evaluating a data signal (DQx) and a data reference signal (DQS), which is switched into the active state (A) by the memory when a memory access occurs during an access cycle, in parallel. The process runs in a tester connected to the memory outputs for the data signal and the data reference signal.

公开(公告)号：DE10011179A1

公开(公告)日：2001-09-20

申请号：DE10011179

申请日：2000-03-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BEER PETER ,  DOBLER MANFRED ,  KRAUSE GUNNAR

IPC: G01K7/01 ,  G01R31/30 ,  H01L23/62 ,  H01L21/66

Abstract: The method involves passing a defined current into selected chip terminals and determining the resultant voltage using a semiconductor diode structure (14) provided between the selected chip terminals. The temperature of the chip is determined based on the determined voltage and current values. The voltage value is extracted directly from the diode structure using a four terminal network connection. The diode semiconductor structure is connected between two chip terminals via connecting lines (13), and is connected to two further chip terminals (12) via two voltage measuring lines (15) using four terminal network connections.