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公开(公告)号：WO03021604A3
公开(公告)日：2003-08-14
申请号：PCT/DE0203058
申请日：2002-08-21
Applicant: INFINEON TECHNOLOGIES AG , CORDES ERIC , EGGERS GEORG ERHARD , LUEPKE JENS , STOCKEN CHRISTIAN
Inventor： CORDES ERIC , EGGERS GEORG ERHARD , LUEPKE JENS , STOCKEN CHRISTIAN
CPC classification number: G11C29/50012 , G11C7/1051 , G11C7/1087 , G11C11/401 , G11C29/50
Abstract: The invention relates to a test method for testing, on a testing device (PA), semiconductor devices (P) that have a bi-directional data strobe link for a data strobe signal (DQS) whereby the data strobe signal is tested by transferring data between the semiconductor memory device (P) to be tested and a second semiconductor memory device of the same type (R). The invention also relates to a device for carrying out the inventive method.
Abstract translation: 用于测试半导体存储器件的方法和装置。 本发明涉及一种用于半导体存储器件的测试方法（P），具有用于一个数据选通信号（DQS）的双向数据选通端，在一个测试装置（PA），数据选通信号的由（要被检查的半导体存储器件之间的数据传送的测试 P）和相同类型的（R）的第二半导体存储器设备中进行，以及用于其的装置。
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公开(公告)号：DE102004060368A1
公开(公告)日：2006-07-06
申请号：DE102004060368
申请日：2004-12-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STOCKEN CHRISTIAN , GANNOUNE YOUSSEF
IPC: G06F11/08 , G06F11/277 , G11C29/04
Abstract: The method involves a number of memory cells which constitute volatile memory. The number of bits are recorded as data sequence in the memory and error correction data is generated from data sequence which detect bit error in the data sequence and error correction data is recorded in the memory. The data sequence and error correction data is scanned from the memory. The data sequence with error correction data is examined for bit errors and an error code is generated from determined bit error. A bit is the modified in its content for the data sequence depending on the control signal. Independent claims are also included for the following: (A) Interface arrangement; and (B) Use of interface arrangement.
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公开(公告)号：DE102004021267A1
公开(公告)日：2005-11-24
申请号：DE102004021267
申请日：2004-04-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STOCKEN CHRISTIAN
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公开(公告)号：DE10344877B3
公开(公告)日：2004-12-30
申请号：DE10344877
申请日：2003-09-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SOMMER MICHAEL BERNHARD , STOCKEN CHRISTIAN
Abstract: The motherboard (10) holds electrical conductors (12) a chip circuit (11) and RAM (Random Access Memory) plug-in sockets (19). The test circuit (1) includes the data storage module to be tested (2). The data storage module has first signal lines (7a-7n) connected to the RAM sockets and second signal lines (8a-8n) connected to the microcontroller (3). The card includes an output circuit (16), an EEPROM (Electrically Erasable Programmable Read-Only Memory 4), a timing signal generator (5) and a voltage source for the interface card (6).
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公开(公告)号：DE10220138A1
公开(公告)日：2003-11-27
申请号：DE10220138
申请日：2002-05-06
Applicant: INFINEON TECHNOLOGIES AG
Inventor： DOBLER MANFRED , STOCKEN CHRISTIAN , HUBER THOMAS
Abstract: A memory device has a carrier substrate (6) with a terminal for supplying a system clock signal (CLK), a number of clock-controlled integrated memory elements (11-18), a sync. device (7) coupled on the input-side with the system clock signal terminal, and a phase-shifter circuit (2-4) as an element of the sync. device (7) by which a phase-shift between the input-side supplied system clock signal (CLK) and the output-side prepared sync. clock signal (Q) is adjusted depending on a control signal (S,S1,S2), the latter being adjusted via an externally programmable memory device (8), coupled with the phase-shifter device. An Independent claim is given for a method of calibrating a memory arrangement.
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Patent Agency Ranking
公开(公告)号：DE10301480A1
公开(公告)日：2004-08-05
申请号：DE10301480
申请日：2003-01-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STOCKEN CHRISTIAN , DOBLER MANFRED , EGGERS GEORG
IPC: H01L23/495 , H05K3/34 , H01L23/50 , H01L21/60 , H01L21/50
Abstract: The method involves one or more stamping process steps in which at least one pin is stamped out of a base body, especially a lead frame. The pin or a section of the pin is coated with a separate metal coating only after final stamping out of the pin. The end face of the outer end section of the pin is also coated with the metal coating. Independent claims are also included for the following: (a) a housing, especially for semiconducting components (b) and a semiconducting component pin.
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公开(公告)号：DE10259300A1
公开(公告)日：2004-07-15
申请号：DE10259300
申请日：2002-12-18
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STOCKEN CHRISTIAN , DOBLER MANFRED
Abstract: Semiconductor component testing method, especially for testing stacked chip modules, has the following steps: writing of a first value to a memory cell of a first semiconductor component; writing of a different value to a memory cell of a second semiconductor component and simultaneous application of a first valve corresponding to the first signal to a pin of the first component and a second value corresponding to the second signal to a pin of the second component. The invention also relates to a corresponding semiconductor test unit and test system.
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公开(公告)号：DE10140986A1
公开(公告)日：2003-03-20
申请号：DE10140986
申请日：2001-08-21
Applicant: INFINEON TECHNOLOGIES AG
Inventor： CORDES ERIC , STOCKEN CHRISTIAN , EGGERS GEORG , LUEPKE JENS
Abstract: The invention relates to a test method for testing, on a testing device (PA), semiconductor devices (P) that have a bi-directional data strobe link for a data strobe signal (DQS) whereby the data strobe signal is tested by transferring data between the semiconductor memory device (P) to be tested and a second semiconductor memory device of the same type (R). The invention also relates to a device for carrying out the inventive method.
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公开(公告)号：DE10137344A1
公开(公告)日：2003-02-20
申请号：DE10137344
申请日：2001-07-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor： CORDES ERIC , STOCKEN CHRISTIAN , EGGERS GEORG
Abstract: A memory circuit includes a plurality of memory cells, an input/output area for addressing or writing onto the plurality of memory cells by means of electrical signals, and an optical-electrical converter for converting optical signals into the electrical signals, the plurality of memory cells and the input/output area being integrated on a chip, and the optical-electrical converter being mechanically connected to the chip or being integrated into the chip.
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公开(公告)号：DE102004060367A1
公开(公告)日：2006-06-29
申请号：DE102004060367
申请日：2004-12-15
Applicant: INFINEON TECHNOLOGIES AG
Inventor： STOCKEN CHRISTIAN , GANNOUNE YOUSSEF
IPC: H01L23/04 , H01L23/02 , H01L23/525 , H01L27/108
Abstract: Chip component (1) has semiconductor body (2). Element, which can be switched, is arranged in sub area (24) of semiconductor body. An integrated switching processed in semiconductor body to take out a configuration (5) from two configurations. A housing (3), which surrounds semiconductor body, has sub area (35) which is arranged partially over sub area of semiconductor body. The housing is formed in such a way that light is conveyed to the sub area of the semiconductor body. An independent claim is also included for a manufacturing method for chip component.
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