公开(公告)号：DE19727466C2

公开(公告)日：2001-12-20

申请号：DE19727466

申请日：1997-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  BERTAGNOLLI EMMERICH

IPC: G11C11/34 ,  G11C11/405 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/401

Abstract: The cell has three transistors e.g. vertical transistors formed on the edges (1F1,1F2,2F2) of trenches (G1,G2) separated alternately by smaller and larger gaps. These facilitate the interconnection of source/drain regions (1S/D1,3S/D2, 2S/D2) of different transistors by contact regions (K). A gate electrode (Ga1) of one transistor is connected to a wordline which is to be read (WA), with the second source or drain region (1S/D2) of this transistor being connected to a bitline (B). The gate electrode (Ga3) of a third transistor is connected to a wordline which is to be written to. The first source or drain region (1S/D1) of the reading transistor is connected to both the second source/drain region of the writing transistor and to which a source/drain region (2S/D2) of a further transistor. The gate (Ga2) of this latter transistor is connected to the source/drain (3S/D1) of the writing transistor and its other source/drain is connected to a power supply.

公开(公告)号：DE19958907A1

公开(公告)日：2001-07-05

申请号：DE19958907

申请日：1999-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  GUTSCHE MARTIN

IPC: B81C1/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/283 ,  H01L27/08 ,  H01G4/33

Abstract: Production of electrodes in a micromechanical or microelectronic device comprises forming a molded support structure in or on a substrate (10); enlarging the surface of the structure; and forming the electrodes (150) using the support structure. Preferred Features: The structure is filled with electrode material using CVD, ALCVD galvanic deposition or a using a spin-on application. The electrode material is Pt, Ir, IrO2, Ru, RuO2, SrxRuyOz, W, WN, WSi, Ta, TaN, Ti, TiN, Mo, MoN or Al.

公开(公告)号：DE10362018B4

公开(公告)日：2007-03-08

申请号：DE10362018

申请日：2003-02-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  MANGER DIRK ,  GOEBEL BERND

IPC: H01L27/105 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

Abstract: The arrangement has rows and columns separated by trenches (5,6) in a transistor cell field in a substrate, active regions (3) between upper (4) and lower (2) source/drain connection regions forming channels controllable by gate electrode potentials. The active regions join at least transistor cells (81) adjacent in the x-direction and charge transport is enabled between the active regions of transistor cells that are adjacent at least in the x-direction. An independent claim is also included for the following: (a) a method of manufacturing vertical transistor cells in a transistor cell field.

公开(公告)号：DE10306281B4

公开(公告)日：2007-02-15

申请号：DE10306281

申请日：2003-02-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLOESSER TILL ,  MANGER DIRK ,  GOEBEL BERND

IPC: H01L27/105 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

Abstract: The arrangement has rows and columns separated by trenches (5,6) in a transistor cell field in a substrate, active regions (3) between upper (4) and lower (2) source/drain connection regions forming channels controllable by gate electrode potentials. The active regions join at least transistor cells (81) adjacent in the x-direction and charge transport is enabled between the active regions of transistor cells that are adjacent at least in the x-direction. An independent claim is also included for the following: (a) a method of manufacturing vertical transistor cells in a transistor cell field.

公开(公告)号：DE10318625B4

公开(公告)日：2006-08-03

申请号：DE10318625

申请日：2003-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  SLESAZECK STEFAN

IPC: H01L27/108 ,  G11C8/02 ,  H01L21/8242

公开(公告)号：DE102004057181A1

公开(公告)日：2006-06-01

申请号：DE102004057181

申请日：2004-11-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  TEMMLER DIETMAR ,  SCHOLZ ARND

IPC: H01L21/8242

Abstract: The method involves providing a storage capacitor in a silicon substrate (100). A poly silicon filling (102) in lower and upper faulty areas is separated from a negative doping layer (104) and the substrate by a memory dielectric layer and an insulator layer (105), respectively. A doping material in the filling is diffused in the substrate in a contact surface area to form a buried conducting connection (106) in the substrate. An independent claim is also included for a method of manufacturing a memory cell in a semiconductor substrate.

公开(公告)号：DE10243380A1

公开(公告)日：2004-04-01

申请号：DE10243380

申请日：2002-09-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

IPC: H01L20060101 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE50000924D1

公开(公告)日：2003-01-23

申请号：DE50000924

申请日：2000-03-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  SCHWARZL SIEGFRIED

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  H01L49/02

Abstract: Layers of metallic lines and layers of memory cells are disposed alternately one above the other. The memory cells each have a diode and a memory element connected in series therewith. The memory element has a layer structure with a magnetoresistive effect. The diode has a layer structure containing at least two metal layers and an insulating layer disposed in between. The layer structure of the memory element and the layer structure of the diode are disposed above one another. The metallic lines of a respective one of the layers run parallel to one another. The metallic lines of mutually adjacent layers run transversely with respect to one another.

公开(公告)号：DE19720193C2

公开(公告)日：2002-10-17

申请号：DE19720193

申请日：1997-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  BERTAGNOLLI EMMERICH

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.