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公开(公告)号:GB2382462A
公开(公告)日:2003-05-28
申请号:GB0216883
申请日:2002-07-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor: ESMARK KAI , GOSSNER HARALD , RIESS PHILIPP , STADLER WOLFGANG , STREIBL MARTIN , WENDEL MARTIN
Abstract: A circuit suitable as an ESD protective element where on occurrence of overvoltage, a low resistance non-destructive path is provided via a semiconductor resistor, which otherwise has a resistance of higher value, for example in a radio-frequency circuit (fig 5). The semiconductor component has a substrate 1, and a cuboid polysilicon strip 10 having electrical contacts 11 and 12. A controllable current source 15 provides the polysilicon strip 10 with a reversible response up to a critical upper current value, the strip having a first differential resistance R diff1 up to a current limit value I t corresponding to an upper voltage limit V 1 , and a second differential resistance R diff2 , less than R diff1 , at current levels above this (fig 2). In second embodiment (fig 4) the semiconductor strip is composed of separate strips of polysilicon (fig 4: 10a-d) having different dopings and lengths.
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公开(公告)号:FR2827706A1
公开(公告)日:2003-01-24
申请号:FR0209195
申请日:2002-07-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor: ESMARK KAI , GOSSNER HARALD , RIESS PHILIPP , STADLER WOLGANG , STREIBL MARTIN , WENDEL MARTIN
IPC: H01L27/04 , H01L21/822 , H01L23/60 , H01L29/74 , H01L23/62
Abstract: The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff 1 ) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff 2 ), which is less than the first differential resistance (Rdiff 1 ).
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公开(公告)号:CA2393668A1
公开(公告)日:2003-01-20
申请号:CA2393668
申请日:2002-07-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor: ESMARK KAI , STADLER WOLFGANG , GOSSNER HARALD , WENDEL MARTIN , STREIBL MARTIN , RIESS PHILIPP
IPC: H01L27/04 , H01L21/822 , H01L23/60 , H01L29/74 , H01L23/52
Abstract: The present invention creates an operating method for a semiconductor component having a substrate (1; 5); having a conductive polysilicon strip (10; l0a-d) which is applied to the substrate (1; 5); having a first and a second electrical contact (11, 12; 11a-d, 12a-d) which are connected to the conductive polysilicon strip (10; 10a-d) such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (R diff1) up to a current limit value (I t) corresponding to an upper voltage limit value (V t) and, at current values greater than this, has a second differential resistance (R diff2), which is less than the first differential resistance (R diff1).
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公开(公告)号:DE10134665C1
公开(公告)日:2002-09-05
申请号:DE10134665
申请日:2001-07-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor: STADLER WOLFGANG , ESMARK KAI , GOSNER HARALD , RIESS PHILIPP , WENDEL MARTIN , STREIBL MARTIN
IPC: H01L27/04 , H01L21/822 , H01L23/60 , H01L29/74 , H01L23/62
Abstract: The operating method provides reversible operation of the semiconductor element in a current/voltage range, with a first differential resistance up to a current limit corresponding to an upper voltage limit and a lesser differential resistance for current values above this current limit. The semiconductor element has a substrate (1,5) with an applied conductive polysilicon strip (10) and a pair of contacts (11,12) coupled to the latter for providing an electrical resistance between them
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公开(公告)号:DE102010017056B4
公开(公告)日:2016-01-21
申请号:DE102010017056
申请日:2010-05-21
Applicant: INFINEON TECHNOLOGIES AG
Inventor: RIESS PHILIPP
Abstract: Halbleiterchip, der einen Kondensator (100) aufweist, wobei der Kondensator (100) enthält: eine erste Elektrode und eine zweite Elektrode, wobei jede Elektrode mehrere erste leitende Streifen (122) aufweist, die sich in einer Längsrichtung erstrecken und in einer Querrichtung nebeneinander angeordnet sind, so dass sich die ersten leitenden Streifen (122A, 122C, 122E) der ersten Elektrode und die ersten leitenden Streifen (122B, 122D, 122F) der zweiten Elektrode in Querrichtung abwechseln, wobei die ersten leitenden Streifen in Längsrichtung länger sind als in Querrichtung, wobei über oder unter jedem der ersten leitenden Streifen (122) ein zweiter leitender Streifen (124) angeordnet ist, der sich in Längsrichtung erstreckt, der in Längsrichtung länger ist als in Querrichtung, der mit dem ersten leitenden Streifen (122) durch wenigstens ein leitendes Kontaktloch (130) elektrisch gekoppelt ist und der kürzer ist als der erste leitende Streifen (122), wobei die über oder unter aneinander angrenzenden ersten leitenden Streifen (122) angeordneten zweiten leitenden Streifen (124) mit einem Abstand in Längsrichtung versetzt zueinander angeordnet sind.
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公开(公告)号:DE10126800B4
公开(公告)日:2010-07-01
申请号:DE10126800
申请日:2001-06-01
Applicant: INFINEON TECHNOLOGIES AG
Inventor: WENDEL MARTIN , OWEN RICHARD , GOSSNER HARALD , STADLER WOLFGANG , RIESS PHILIPP , STREIBL MARTIN , ESMARK KAI
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公开(公告)号:DE102009000625A1
公开(公告)日:2009-10-01
申请号:DE102009000625
申请日:2009-02-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: KALTALIOGLU ERDEM , RIESS PHILIPP , WENDT HERMANN
IPC: H01L21/768 , H01L21/311 , H01L21/3205 , H01L23/52
Abstract: Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.
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公开(公告)号:DE102009000627A1
公开(公告)日:2009-09-24
申请号:DE102009000627
申请日:2009-02-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER ARMIN , RIESS PHILIPP
IPC: H01L27/08 , H01L21/3205 , H01L21/82 , H01L29/92
Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.
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公开(公告)号:DE102005047409A1
公开(公告)日:2007-04-12
申请号:DE102005047409
申请日:2005-10-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: BAUMGARTNER PETER , BENETIK THOMAS , DRAXELMAYR DIETER , RIESS PHILIPP
IPC: H01L27/08
Abstract: The semiconductor component has an integrated capacitance structure with several strip elements (SE) of which a first group represents a first electrode and a second group a second electrode. The first and second strip elements intermesh with each other at least partially and at least one strip element has a non-constant cross-sectional surface area. This strip element can have a tapering cross-section to form a wedge : The strip elements can be formed in several metal plated planes of the component.
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公开(公告)号:DE102005028919A1
公开(公告)日:2006-12-28
申请号:DE102005028919
申请日:2005-06-22
Applicant: INFINEON TECHNOLOGIES AG
Inventor: RIESS PHILIPP , WENDEL MARTIN , FEICK HENNING
Abstract: An electronic component comprises: a doped substrate; at least one connection region formed in the doped substrate; at least one additional doped region formed in the doped substrate at least below the at least one connection region, where the at least one doped region is formed as an electrostatic discharges (ESD) region for protection against electrostatically generated discharges; at least one well region formed in the doped substrate, where the well region is formed in such a way that the well region doping is blocked at least below the at least one doped region. An independent claim is included for producing the electronic component involving: doping the substrate with doping atoms to form forming at least one connection region of the electronic component in the substrate; doping the substrate with doping atoms to form at least one doped region in the substrate located at least below the at least one connection region; and doping the substrate with doping atoms to form at least one well region in the substrate, where the well region doping is blocked at least below the at least one doped region in such a way that the doping intensity in each region blocked from the well region doping corresponds to the doping intensity of the substrate or remains unchanged until the end of the production of the electronic component.
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