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    DRIVING METHOD FOR SEMICONDUCTOR ELEMENT
    1.
    发明专利
    DRIVING METHOD FOR SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：JP2003133428A

    公开(公告)日：2003-05-09

    申请号：JP2002209383

    申请日：2002-07-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

    IPC: H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/74

    Abstract: PROBLEM TO BE SOLVED: To provide a driving method for a semiconductor element which is integrated into a VLSI process readily. SOLUTION: The semiconductor has a substrate (1; 5), a conductive strip (10; 10a to d) which is arranged to the substrate (1; 5), and first and second electrical contacts (11, 12; 11a to d, 12a to d) which are connected to a polysilicon conductor strip (10; 10a to d) to form an electrical resistance between them. A semiconductor element is driven reversibly in a fixed current/voltage range. In the current/voltage range, a semiconductor element has a first differential resistance (Rdiff1 ) up to and including a current limit value (It ) corresponding to an upper voltage limit value (Vt ) and, at current values greater than the current limit value, it has a second differential resistance (Rdiff2 ) which is less than the first differential resistance (Rdiff1 ).

    METHOD FOR DETERMINING THE ESD/LATCH-UP RESISTANCE OF AN INTEGRATED CIRCUIT
    2.
    发明申请
    METHOD FOR DETERMINING THE ESD/LATCH-UP RESISTANCE OF AN INTEGRATED CIRCUIT 审中-公开
    确定集成电路ESD /闩锁上拉强度的方法

    公开(公告)号：WO03052824A2

    公开(公告)日：2003-06-26

    申请号：PCT/DE0204599

    申请日：2002-12-16

    Applicant: INFINEON TECHNOLOGIES AG ,  BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

    Inventor： BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

    IPC: H01L23/544 ,  H01L23/60 ,  H01L27/00

    CPC classification number: H01L22/34 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: The invention relates to a method for determining the ESD/latch-up resistance of an integrated circuit, said method comprising the following steps: an integrated circuit (1, 2) and a test structure (N3) are simultaneously produced by means of the same process steps; electrical parameters of the test structure (N3) are measured; characteristic values are derived from the measured parameter values, said characteristic values characterising an ESD or latch-up characteristic curve associated with the integrated circuit (1, 2); and it is checked whether the characteristic values are respectively contained in a pre-determined range associated with the same. The ranges are selected in such a way that a desired ESD/latch-up resistance is achieved when the characteristic values are respectively contained in their range.

    Abstract translation: 一种用于确定集成电路的ESD /闭锁强度等，其包括以下步骤的方法：共享通过相同的工艺步骤制造集成电路（1,2）和一个测试结构（N3），在该测试结构（N3）的电气参数的测量， 从所测量的参数值，其中所述集成电路中的一个的特征值（1，2）与ESD相关联或表征闩锁的特性曲线导出特征值，并且检查所述参数是否内的分配给它们的预定范围内的每个，所述区域 被选择为使得如果特性各自在它们的范围内，则存在期望的ESD /闭锁强度。

    ESD- und EMC-optimierter MOS-Transistor
    4.
    发明专利
    ESD- und EMC-optimierter MOS-Transistor 未知

    公开(公告)号：DE102011002198A1

    公开(公告)日：2011-12-15

    申请号：DE102011002198

    申请日：2011-04-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ESMARK KAI ,  MUELLER KARLHEINZ

    IPC: H01L23/60 ,  H01L25/11

    Abstract: Es werden hier Anordnungen und Schaltungen in Bezug auf elektrostatische Entladung (ESD) und elektromagnetische Verträglichkeit (EMC) beschrieben. Eine ESD-Schutzanordnung wird in einen Transistor integriert, um das Gate des Transistors vor übermäßigen Stromlasten in Bezug auf ESD- oder EMC-Ereignisse zu schützen. Bei einer Implementierung umfasst eine Anordnung eine erste Diode (508) und eine zweite Diode (512), die über ihre jeweiligen Katoden elektrisch verbunden sind. Die Durchschlagspannung der ersten Diode (508) ist niedriger als die Durchschlagspannung der zweiten Diode (512), um übermäßigen Strom durch die zweite Diode (512) umzuleiten.

    9.
    发明专利
    未知

    公开(公告)号：DE102008005932A1

    公开(公告)日：2008-08-14

    申请号：DE102008005932

    申请日：2008-01-24

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUSS CORNELIUS CHRISTIAN ,  ESMARK KAI ,  ALVAREZ DAVID ,  SCHNEIDER JENS

    IPC: H01L23/60

    Abstract: A semiconductor device includes an ESD device region disposed within a semiconductor body of a first semiconductor type, an isolation region surrounding the ESD device region, a first doped region of a second conductivity type disposed at a surface of the semiconductor body within the ESD region, and a second doped region of the first conductivity type disposed between the semiconductor body within the ESD region and at least a portion of the first doped region, where the doping concentration of the second doped region is higher than the semiconductor body. A third doped region of the second semiconductor type is disposed on the semiconductor body and a fourth region of the first conductivity type is disposed over the third doped region. A fifth doped region of the second conductivity type is disposed on the semiconductor body. A trigger device and an SCR is formed therefrom.

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