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    DRIVING METHOD FOR SEMICONDUCTOR ELEMENT
    1.
    发明专利
    DRIVING METHOD FOR SEMICONDUCTOR ELEMENT 审中-公开

    公开(公告)号：JP2003133428A

    公开(公告)日：2003-05-09

    申请号：JP2002209383

    申请日：2002-07-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

    IPC: H01L27/04 ,  H01L21/822 ,  H01L23/60 ,  H01L29/74

    Abstract: PROBLEM TO BE SOLVED: To provide a driving method for a semiconductor element which is integrated into a VLSI process readily. SOLUTION: The semiconductor has a substrate (1; 5), a conductive strip (10; 10a to d) which is arranged to the substrate (1; 5), and first and second electrical contacts (11, 12; 11a to d, 12a to d) which are connected to a polysilicon conductor strip (10; 10a to d) to form an electrical resistance between them. A semiconductor element is driven reversibly in a fixed current/voltage range. In the current/voltage range, a semiconductor element has a first differential resistance (Rdiff1 ) up to and including a current limit value (It ) corresponding to an upper voltage limit value (Vt ) and, at current values greater than the current limit value, it has a second differential resistance (Rdiff2 ) which is less than the first differential resistance (Rdiff1 ).

    METHOD FOR DETERMINING THE ESD/LATCH-UP RESISTANCE OF AN INTEGRATED CIRCUIT
    2.
    发明申请
    METHOD FOR DETERMINING THE ESD/LATCH-UP RESISTANCE OF AN INTEGRATED CIRCUIT 审中-公开
    确定集成电路ESD /闩锁上拉强度的方法

    公开(公告)号：WO03052824A2

    公开(公告)日：2003-06-26

    申请号：PCT/DE0204599

    申请日：2002-12-16

    Applicant: INFINEON TECHNOLOGIES AG ,  BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

    Inventor： BARGSTAEDT-FRANKE SILKE ,  ESMARK KAI ,  GOSSNER HARALD ,  RIESS PHILIPP ,  STADLER WOLFGANG ,  STREIBL MARTIN ,  WENDEL MARTIN

    IPC: H01L23/544 ,  H01L23/60 ,  H01L27/00

    CPC classification number: H01L22/34 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: The invention relates to a method for determining the ESD/latch-up resistance of an integrated circuit, said method comprising the following steps: an integrated circuit (1, 2) and a test structure (N3) are simultaneously produced by means of the same process steps; electrical parameters of the test structure (N3) are measured; characteristic values are derived from the measured parameter values, said characteristic values characterising an ESD or latch-up characteristic curve associated with the integrated circuit (1, 2); and it is checked whether the characteristic values are respectively contained in a pre-determined range associated with the same. The ranges are selected in such a way that a desired ESD/latch-up resistance is achieved when the characteristic values are respectively contained in their range.

    Abstract translation: 一种用于确定集成电路的ESD /闭锁强度等，其包括以下步骤的方法：共享通过相同的工艺步骤制造集成电路（1,2）和一个测试结构（N3），在该测试结构（N3）的电气参数的测量， 从所测量的参数值，其中所述集成电路中的一个的特征值（1，2）与ESD相关联或表征闩锁的特性曲线导出特征值，并且检查所述参数是否内的分配给它们的预定范围内的每个，所述区域 被选择为使得如果特性各自在它们的范围内，则存在期望的ESD /闭锁强度。

    6.
    发明专利
    未知

    公开(公告)号：DE102005028919A8

    公开(公告)日：2007-05-31

    申请号：DE102005028919

    申请日：2005-06-22

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RIESS PHILIPP ,  WENDEL MARTIN ,  FEICK HENNING

    IPC: H01L23/60 ,  H01L29/78

    Abstract: An electronic component comprises: a doped substrate; at least one connection region formed in the doped substrate; at least one additional doped region formed in the doped substrate at least below the at least one connection region, where the at least one doped region is formed as an electrostatic discharges (ESD) region for protection against electrostatically generated discharges; at least one well region formed in the doped substrate, where the well region is formed in such a way that the well region doping is blocked at least below the at least one doped region. An independent claim is included for producing the electronic component involving: doping the substrate with doping atoms to form forming at least one connection region of the electronic component in the substrate; doping the substrate with doping atoms to form at least one doped region in the substrate located at least below the at least one connection region; and doping the substrate with doping atoms to form at least one well region in the substrate, where the well region doping is blocked at least below the at least one doped region in such a way that the doping intensity in each region blocked from the well region doping corresponds to the doping intensity of the substrate or remains unchanged until the end of the production of the electronic component.

    9.
    发明专利
    未知

    公开(公告)号：DE102004009981A1

    公开(公告)日：2005-09-22

    申请号：DE102004009981

    申请日：2004-03-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STREIBL MARTIN ,  ESMARK KAI ,  RUSS CHRISTIAN ,  WENDEL MARTIN ,  GOSNER HARALD

    IPC: H01L23/60 ,  H02H9/00 ,  H02H9/02

    Abstract: An ESD protective circuit protects an input or output of a monolithically integrated circuit. The ESD protective circuit has at least one bipolar transistor structure and one ESD protective element between two supply networks. The emitter of the bipolar transistor structure is electrically connected to the input or output, while the base is electrically connected to one of the two supply networks. The collector produces a current signal, which is used for triggering of the ESD protective element, when an ESD load occurs at the input or output.

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