中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

54 records (took 0.087 seconds)

    Synchronous integrated memory e.g. for SGRAM
    21.
    发明专利
    Synchronous integrated memory e.g. for SGRAM 未知

    公开(公告)号：DE19933540A1

    公开(公告)日：2001-04-19

    申请号：DE19933540

    申请日：1999-07-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHROEGMEIER PETER ,  PARTSCH TORSTEN ,  DIETRICH STEFAN ,  WEIS CHRISTIAN

    IPC: G11C7/10 ,  G11C7/00

    Abstract: The memory includes data lines (DL) via which data terminals (DPi) are connected through a synchronising unit (SY) to groups (G1,G2) of memory cells. The synchronising unit is adjacent to cell group G1 and comprises a clock input to which an internal clock (CLKI) is supplied. During a write access to the memory, the synchronising unit synchronises data signals fed to the data terminals (DPi) - which are synchronous with an external clock (CLKE) - with the internal clock.

    23.
    发明专利
    未知

    公开(公告)号：DE10149584B4

    公开(公告)日：2007-11-22

    申请号：DE10149584

    申请日：2001-10-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： MILLER THOMAS ,  HEYNE PATRICK ,  WEIS CHRISTIAN

    IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  H03D3/24 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03L7/081

    Abstract: A delay locked loop includes a first delay device for obtaining a fine setting and a downstream-connected second delay device for obtaining a coarse setting of the delay time. The control signals for controlling the respective delay devices are provided by synchronization latches, which receive a clock obtained by the output signal of the first delay device for obtaining the fine setting. The delay locked loop enables a linear operating behavior at a high operating frequency and is particularly suitable when a differential embodiment of the two delay devices is used.

    25.
    发明专利
    未知

    公开(公告)号：DE19924288B4

    公开(公告)日：2006-08-31

    申请号：DE19924288

    申请日：1999-05-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DIETRICH STEFAN ,  SCHROEGMEIER PETER ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

    IPC: G11C7/00 ,  G11C7/06 ,  G11C7/18

    Abstract: An integrated memory has a first operating mode, in which, during each write access, only one of the two global amplifiers is active and transmits a datum via one of the local amplifiers to the corresponding bit line. Moreover, the memory has a second operating mode, in which, during each write access, both global amplifiers are simultaneously active and transmit a common datum via in each case at least one of the local amplifiers to the corresponding bit lines.

    27.
    发明专利
    未知

    公开(公告)号：DE10116914B4

    公开(公告)日：2005-08-04

    申请号：DE10116914

    申请日：2001-04-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN

    IPC: G11C7/10 ,  G11C7/22

    Abstract: The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

    28.
    发明专利
    未知

    公开(公告)号：DE10200898B4

    公开(公告)日：2004-12-09

    申请号：DE10200898

    申请日：2002-01-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  WEIS CHRISTIAN ,  ACHARYA PRAMOD

    IPC: H03K5/00 ,  H03K5/13 ,  G11C29/00

    Abstract: An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

Patent Agency Ranking