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    INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME
    21.
    发明申请
    INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME 审中-公开
    互连结构及其制造方法

    公开(公告)号：WO2006113186A3

    公开(公告)日：2008-07-24

    申请号：PCT/US2006013179

    申请日：2006-04-07

    Applicant: IBM ,  YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

    Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

    IPC: H01L21/4763

    CPC classification number: H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

    Abstract translation: 一种镶嵌线及其形成方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。 该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

    MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME
    22.
    发明申请
    MICRO-CAVITY MEMS DEVICE AND METHOD OF FABRICATING SAME 审中-公开
    微孔MEMS器件及其制造方法

    公开(公告)号：WO2007027813A3

    公开(公告)日：2007-12-06

    申请号：PCT/US2006033924

    申请日：2006-08-30

    Applicant: IBM ,  HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

    Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

    IPC: H01P1/10

    CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

    Abstract: A MEM switch is described having a free moving element (140) within in micro-cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180,200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_I M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When gravity cannot be used, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

    Abstract translation: 描述了一种MEM开关，其具有在微腔（40）内的自由移动元件（140），并由至少一个电感元件引导。 开关由上部感应线圈（170）组成; 可选的下感应线圈（190），每个具有优选由坡莫合金制成的金属芯（180,200） 微腔（40）; 以及也由磁性材料制成的自由移动的开关元件（140）。 通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。 磁场向上吸引自由移动的磁性元件，使两根开放的导线（M_I M_r）短路，从而闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。 当不能使用重力时，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

    VERGRABENE METALL-SIGNALSCHIENE FÜR SPEICHERARRAYS
    23.
    发明专利
    VERGRABENE METALL-SIGNALSCHIENE FÜR SPEICHERARRAYS 未知

    公开(公告)号：DE112023002938T5

    公开(公告)日：2025-05-15

    申请号：DE112023002938

    申请日：2023-09-05

    Applicant: IBM

    Inventor： SENAPATI BISWANATH ,  MUNETOH SEIJI ,  LANZILLO NICHOLAS ANTHONY ,  CLEVENGER LAWRENCE A ,  BURR GEOFFREY ,  HOSOKAWA KOHJI

    IPC: H10B63/10 ,  H01L21/768 ,  H01L23/52

    Abstract: Eine IC-Speichereinheit enthält ein Substrat und ein Array von Speicherzellen auf dem Substrat. Jede Speicherzelle enthält wenigstens einen Speicherzellentransistor in einer Schicht der Einheit benachbart zu dem Substrat. In der gleichen Schicht enthält die Einheit ferner eine Mehrzahl von Nebenschlusstransistoren. Die Einheit enthält ferner eine vergrabene Metall-Signalschiene, die zwischen dem Array von Speicherzellen und der Mehrzahl von Nebenschlusstransistoren in einer vergrabenen Schicht angeordnet ist, die unter den Transistoren in dem Substrat eingebettet ist. Die Einheit enthält ferner Einzelschicht-Durchkontaktierungen, die in der gleichen Schicht wie die Transistoren angeordnet sind und die Speicherzellentransistoren durch die vergrabene Metall-Signalschiene elektrisch mit den Nebenschlusstransistoren verbinden.

    Mosfet and method for manufacturing the same
    27.
    发明专利
    Mosfet and method for manufacturing the same 有权
    MOSFET及其制造方法

    公开(公告)号：JP2003023155A

    公开(公告)日：2003-01-24

    申请号：JP2002127052

    申请日：2002-04-26

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS L ,  RADENS CARL J ,  SHEPARD JOSEPH F JR

    IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L21/28176 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/517

    Abstract: PROBLEM TO BE SOLVED: To provide a MOSFET(metal oxide semiconductor field effect transistor) and a method for manufacturing the MOSFET capable of eliminating the overlap of a gate dielectric and a source/drain region with high reliability.
    SOLUTION: This method for manufacturing a MOSFET comprises the process of patterning a gate laminate constituted of a gate dielectric 20 arid a gate conductor 30 formed on a substrate 10, and the process of modifying the gate dielectric 20 beneath the gate dielectric 30 so that the gate dielectric 20 can have a central portion and a modified dielectric region 70 adjacent to the central portion. The modified dielectric region 70 has a lower dielectric constant than that of the gate dielectric 20, and the central portion is shorter than the gate conductor 30.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供一种MOSFET（金属氧化物半导体场效应晶体管）以及能够以高可靠性消除栅极电介质和源极/漏极区域的重叠的MOSFET的制造方法。 解决方案：用于制造MOSFET的方法包括对由栅极电介质20和形成在衬底10上的栅极导体30构成的栅极叠层的图案化以及在栅极电介质30下面改变栅极电介质20的工艺， 栅极电介质20可以具有与中心部分相邻的中心部分和改进的电介质区域70。 改性电介质区域70具有比栅极电介质20低的介电常数，并且中心部分比栅极导体30短。

    METHOD OF FORMING DUAL-DAMASCENE INTERCONNECTION AND STRUCTURE USING THE METHOD
    28.
    发明专利
    METHOD OF FORMING DUAL-DAMASCENE INTERCONNECTION AND STRUCTURE USING THE METHOD 审中-公开

    公开(公告)号：JP2002289691A

    公开(公告)日：2002-10-04

    申请号：JP2002021019

    申请日：2002-01-30

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE A ,  NESBIT LARRY A

    IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide a structure and method of forming a dual-damascene structure. SOLUTION: The method (and structure) of forming interconnection on a semiconductor substrate includes a step for forming a relatively narrow first structure in a dielectric material formed on the semiconductor substrate, a step for forming a relatively wide second structure in the dielectric material formed on the semiconductor substrate, a step for forming a liner in the first and second structure so that the first structure is substantially filled with the liner and the second structure is not substantially filled, with the liner and a step for metallizing the liner to completely fill the second structure.

    INTEGRATED CIRCUIT
    29.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11330244A

    公开(公告)日：1999-11-30

    申请号：JP9247299

    申请日：1999-03-31

    Applicant: SIEMENS AG ,  IBM

    Inventor： CLEVENGER LAWRENCE A ,  FILIPPI RONALD G ,  HOINKIS MARK ,  HURD JEFFERY L ,  IGGULDEN ROY C ,  PALM HERBERT ,  POETZLBERGER HANS W ,  RODBELL KENNETH P ,  SCHNABEL FLORIAN ,  WEBER STEFAN ,  MEHTER EBRAHIM A

    IPC: H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnection with a damascene structure having an improved reliability, by using a liner for surrounding or sealing a conductor to give random crystal grain orientation to a conductive material. SOLUTION: A layer 137 is deposited on an insulating layer 130. A layer for lining the wall and the bottom of the contact opening functions as a base coat or liner for a conductive layer 138 to be subsequently deposited to fill the contact opening, and the degree of crystal grain orientation randomness of a material that fills the damascene structure is expanded. A parameter used for depositing a TiN layer is selected to expand the degree of base coat crystal grain orientation randomness and/or amorphous characteristics. The liner has an enough thickness to ensure the random crystal grain orientation of the conductive material to be subsequently deposited. Thus, the interconnection in an IC having the improved reliability can be obtained.

    METHOD OF FORMING NANO-SCALE STRUCTURES FROM POLYCRYSTALLINE MATERIALS AND NANO-SCALE STRUCTURES FORMED THEREBY
    30.
    发明专利
    METHOD OF FORMING NANO-SCALE STRUCTURES FROM POLYCRYSTALLINE MATERIALS AND NANO-SCALE STRUCTURES FORMED THEREBY 未知

    公开(公告)号：MY120870A

    公开(公告)日：2005-11-30

    申请号：MYPI20011041

    申请日：2001-03-07

    Applicant: IBM

    Inventor： NAEEM MUNIR D ,  CLEVENGER LAWRENCE A

    IPC: H01L21/28 ,  H01L21/768

    Abstract: A METHOD OF FORMING NANO-SCALE FEATURES WITH CONVENTIONAL MULTILAYER STRUCTURE, AND NANO-SCALE FEATURES FORMED THEREBY. THE METHOD GENERALLY ENTAILS FORMING A MULTILAYER STRUCTURE THAT INCLUDES A POLYCRYSTALLINE LAYER AND AT LEAST ONE CONSTRAINING LAYER. THE MULTILAYER STRUCTURE IS PATTERNED TO FORM FIRST AND SECOND STRUCTURES, EACH OF WHICH INCLUDES THE POLYCRYSTALLINE AND CONSTRAINING LAYERS. AT LEAST THE FIRST STRUCTURE IS THEN LOCALLY HEATED, DURING WHICH TIME THE CONSTRAINING LAYER RESTRICTS THE THERMAL EXPANSION OF THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE. AS A RESULT, STRESSES ARE INDUCED IN THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE. AS A RESULT, STRESSES ARE INDUCED IN THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE, CAUSING SUBSTANTIALLY TWO-DIMENSIONAL GRAIN GROWTH FROM THE EDGE OF THE FIRST STRUCTURE. SUFFICIENT GRAIN GROWTH OCCURS TO PRODUCE A THIRD STRUCTURE WHICH, BASED ON THE GRAIN SIZE OF THE POLYCRYSTALLINE LAYER, WILL BE A NANO-SCALE STRUCTURE. WHEN APPROPRIATELY CONFIGURED, NANO-SCALE STRUCTURES CAN BE FORMED AS OPERATIVE COMPONENTS OF ELECTRICAL, MENCHANICAL, OPTICAL AND FLUID-HANDLING DEVICES.

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