Abstract:
A method of preventing or at least reducing the likelihood of bridging (20) between adjacent micro-scale polycrystalline structures, and particularly to reducing electrical shorting between adjacent metallization lines of a microcircuit. The method generally entails forming a multilayer structure that comprises a polycrystalline layer (12) and at least one constraining layer (14), and then patterning the multilayer structure to yield a first line (16) and a second line (18) that is narrower in width than the first line. The first line has a patterned edge (24) that is spaced apart from a patterned edge (26) of the second line, so that the first and second lines are electrically insulated from each other. One or more features associated with the first line are then formed that prevent bridging between the first and second lines if excessive lateral grain growth subsequently occurs along the patterned edge of the first line.
Abstract:
PROBLEM TO BE SOLVED: To provide a method of minimizing an RIE lag, which occurs during production of a DT in a DRAM having a large aspect ratio. SOLUTION: Using this method, isotropic etching of a wafer can be prevented and hence a passivation film is formed to such a extent as to require to maintain a profile and shape of a DT in the wafer. The RIE process described here provides a partial DT etched in the wafer to attain a prescribed depth. This passivation film is grown to a certain thickness which is not sufficiently thick to block an opening of the deep-trench. In an alternative method, the passivation film is removed by a non-RIE process. The non-RIE process for removing the film may be wet etching using chemicals, such as hydrofluoric acid (buffered or unbuffered) or the like. Alternatively, a vapor phase of hydrofluoric anhydride or the like and/or un-ionized chemicals may be used. By controlling the film thickness, a prescribed depth of a DT for a high aspect ratio structure can be obtained.
Abstract:
PROBLEM TO BE SOLVED: To easily remove the polymer deposition generated during etching by applying high sputtering component etching to at least a part of a first barrier layer and further low sputtering component etching to at least a part of a metallic treatment layer, respectively. SOLUTION: The high sputtering component etching advantageously increases the sputtering of a photoresist layer, allows additive carbon to exist in an etching reactor and this carbon to be absorbed in the side wall deposition. This deposition is made more soluble by increasing the carbon quantity of the side wall deposition and may be made easily removable during the subsequent photoresist stripping and washing stage. The metal treatment layer is usually substantially thicker than the apex barrier layer of most of the laminates and, therefore, the use of the low sputtering component etching to etch the metal treatment layer in order to lessen photoresist corrosion is recommended.
Abstract:
A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.
Abstract:
PROBLEM TO BE SOLVED: To provide a method for forming a collar oxide in the trench of a semiconductor substrate by selectively etching a conformal oxide layer. SOLUTION: In a semiconductor substrate 1 having (1) a trench 100, (2) (i) the filler surface demarcated by filler material for partially filling the trench 100, (ii) the upper surface outside the trench 100, and (iii) part of a sidewall of the trench which is not covered by the filler material, and (3) a conformal oxide layer formed on the upper surface, the sidewall, and the filler surface, (a) the substrate 1 is brought into contact with a mixture of hydrogen-containing fluorocarbon and a source of oxygen under the reactive ion etching conditions, and then (b) the substrate 1 is brought into contact with a mixture of fluorocarbon which does not contain hydrogen and gas for dilution under the reactive ion etching conditions, and the upper surface and the filler surface are selectively overetched while most of the conformal oxide is left over on the sidewall of the trench to form a collar oxide 41.
Abstract:
PROBLEM TO BE SOLVED: To make more vertical sidewall shape while reducing the corrosion by a method wherein aluminum and aluminum alloy are anisotropically etched away by RIE using specific low power and pressure. SOLUTION: In the title process, aluminum and aluminum alloy are anisotropically etched away by RIE using low power (not exceeding 350W) and low pressure (not exceeding 15mT). Within an upper layer 14 and a bottom layer 10, the physical etching process called sputtering is performed while in a bulk aluminum layer 12, the chemical process is performed. As for the reaction gas of RIE, chlorine, HCl and inert gas (e.g. nitrogen, argon, helium, etc.) are enumerated. Through these procedures, the corrosion of sidewall and the other problems posed by high power RIE can be solved. Besides, a photoresist 16 can be removed more easily while it is released.
Abstract:
A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.
Abstract:
A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., > 30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures
Abstract:
A METHOD OF FORMING NANO-SCALE FEATURES WITH CONVENTIONAL MULTILAYER STRUCTURE, AND NANO-SCALE FEATURES FORMED THEREBY. THE METHOD GENERALLY ENTAILS FORMING A MULTILAYER STRUCTURE THAT INCLUDES A POLYCRYSTALLINE LAYER AND AT LEAST ONE CONSTRAINING LAYER. THE MULTILAYER STRUCTURE IS PATTERNED TO FORM FIRST AND SECOND STRUCTURES, EACH OF WHICH INCLUDES THE POLYCRYSTALLINE AND CONSTRAINING LAYERS. AT LEAST THE FIRST STRUCTURE IS THEN LOCALLY HEATED, DURING WHICH TIME THE CONSTRAINING LAYER RESTRICTS THE THERMAL EXPANSION OF THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE. AS A RESULT, STRESSES ARE INDUCED IN THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE. AS A RESULT, STRESSES ARE INDUCED IN THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE, CAUSING SUBSTANTIALLY TWO-DIMENSIONAL GRAIN GROWTH FROM THE EDGE OF THE FIRST STRUCTURE. SUFFICIENT GRAIN GROWTH OCCURS TO PRODUCE A THIRD STRUCTURE WHICH, BASED ON THE GRAIN SIZE OF THE POLYCRYSTALLINE LAYER, WILL BE A NANO-SCALE STRUCTURE. WHEN APPROPRIATELY CONFIGURED, NANO-SCALE STRUCTURES CAN BE FORMED AS OPERATIVE COMPONENTS OF ELECTRICAL, MENCHANICAL, OPTICAL AND FLUID-HANDLING DEVICES.