公开(公告)号：GB2377529B

公开(公告)日：2004-10-27

申请号：GB0224460

申请日：2001-01-16

Applicant: INTEL CORP

Inventor： LEE CHAN W ,  HINTON GLENN ,  KRICK ROBERT

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/50 ,  G06F12/12 ,  G06F12/08

Abstract: A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.

公开(公告)号：GB2377529A

公开(公告)日：2003-01-15

申请号：GB0224460

申请日：2001-01-16

Applicant: INTEL CORP

Inventor： LEE CHAN W ,  HINTON GLENN ,  KRICK ROBERT

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/50 ,  G06F12/12 ,  G06F12/08

Abstract: A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread.

公开(公告)号：GB2261087A

公开(公告)日：1993-05-05

申请号：GB9222512

申请日：1992-10-27

Applicant: INTEL CORP

Inventor： HINTON GLENN ,  TIWARY GYANENDRA

IPC: G06F9/355 ,  G06F12/10

Abstract: A processor includes a mechanism in which logical addresses are translated into physical addresses by a translation lookaside buffer (TLB) 11 within one clock cycle. This is achieved by the TLB translation being performed in parallel with the calculation of the effective address, the effective address being calculated by a "base-plus-displacement/offset" computation. Such a computation usually does not cross a page boundary, that is, the upper 20 bits, which correspond to the logical page number, are the same after the add. Therefore, only the upper 20 bits of the logical address are translated by the TLB, since it is assumed that these will not change. After the add, if the upper 20 bits did not change, then the 20 physical address bits from the TLB plus the lower 12 bits from the address computation are concatenated to produce the complete correct 32-bit physical address within a single clock cycle. If, however, the upper 20 bits did not change then a signal is generated which enables the translation using the correct logical address, as computed by the effective address generation hardware, to be performed.

公开(公告)号：GB2510760A

公开(公告)日：2014-08-13

申请号：GB201408834

申请日：2011-12-20

Applicant: INTEL CORP

Inventor： RAMANUJAN RAJ K ,  HINTON GLENN ,  ZIMMERMAN DAVID J

IPC: G06F12/08

Abstract: A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC.

公开(公告)号：GB2473149A

公开(公告)日：2011-03-02

申请号：GB201015976

申请日：2009-06-09

Applicant: INTEL CORP

Inventor： JUENEMANN DALE J ,  HOWES JORDAN ,  MATTHEWS JEANNA ,  WELLS STEVEN ,  HINTON GLENN ,  PINTO OSCAR P ,  TETRICK RAYMOND SCOTT

IPC: G06F12/08 ,  G06F13/16

Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

公开(公告)号：DE602006003912D1

公开(公告)日：2009-01-08

申请号：DE602006003912

申请日：2006-08-03

Applicant: INTEL CORP

Inventor： ROTHMAN MICHAEL ,  ZIMMER VINCENT ,  HINTON GLENN ,  DORAN MARK ,  KINNEY MICHAEL

IPC: G06F9/445

公开(公告)号：AT415654T

公开(公告)日：2008-12-15

申请号：AT06789443

申请日：2006-08-03

Applicant: INTEL CORP

Inventor： ROTHMAN MICHAEL ,  ZIMMER VINCENT ,  HINTON GLENN ,  DORAN MARK ,  KINNEY MICHAEL

IPC: G06F9/445

公开(公告)号：AU2956701A

公开(公告)日：2001-10-23

申请号：AU2956701

申请日：2001-01-16

Applicant: INTEL CORP

Inventor： LEE CHAN W ,  HINTON GLENN ,  KRICK ROBERT

IPC: G06F9/318 ,  G06F9/38 ,  G06F9/50 ,  G06F12/12 ,  G06F9/46

Abstract: A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.

公开(公告)号：DE3716229C2

公开(公告)日：1996-08-14

申请号：DE3716229

申请日：1987-05-14

Applicant: INTEL CORP

Inventor： MEYERS GLENFORD J ,  LAI KONRAD ,  IMEL MICHAEL T ,  HINTON GLENN ,  RICHES ROBERT

IPC: G06F9/42 ,  G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F12/08 ,  G06F9/34

Abstract: A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

公开(公告)号：GB2287334A

公开(公告)日：1995-09-13

申请号：GB9416273

申请日：1994-08-11

Applicant: INTEL CORP

Inventor： BRAYTON JAMES M ,  RHODEHAMEL MICHAEL W ,  SARANGDHAR NITIN V ,  HINTON GLENN

IPC: G06F9/38 ,  G06F12/08 ,  G06F13/18

Abstract: A computer system having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue and associated mechanism, which cooperate to monitor and control the issuance of, and the order of, data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.