公开(公告)号：DE112006001636T5

公开(公告)日：2008-05-08

申请号：DE112006001636

申请日：2006-06-30

Applicant: INTEL CORP

Inventor： TRIKA SANJEEV ,  FABERT ROBERT ,  COULSON RICK ,  MATTHEWS JEANNA

IPC: G06F12/02

Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

公开(公告)号：WO2009158183A3

公开(公告)日：2010-02-25

申请号：PCT/US2009046731

申请日：2009-06-09

Applicant: INTEL CORP ,  TETRICK R SCOTT ,  JUENEMANN DALE ,  HOWES JORDAN ,  MATTHEWS JEANNA ,  WELLS STEVEN ,  HINTON GLENN ,  PINTO OSCAR

Inventor： TETRICK R SCOTT ,  JUENEMANN DALE ,  HOWES JORDAN ,  MATTHEWS JEANNA ,  WELLS STEVEN ,  HINTON GLENN ,  PINTO OSCAR

IPC: G06F12/08 ,  G06F13/16

CPC classification number: G06F12/0868 ,  G06F12/0888 ,  G06F2212/222 ,  Y02D10/13

Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

Abstract translation: 在一些实施例中，电子系统可以包括位于大容量存储器和系统存储器之间的高速缓存器，以及存储在电子系统上的代码，以防止流数据在高速缓存中的存储并且直接在系统存储器和 基于对第一信息的第一请求的第一元数据和先前引导上下文中存储的预引导流信息的比较的大容量存储。 公开和要求保护其他实施例。

公开(公告)号：DE112009000418T5

公开(公告)日：2011-04-21

申请号：DE112009000418

申请日：2009-06-09

Applicant: INTEL CORP

Inventor： TETRICK SCOTT R ,  JUENEMANN DALE ,  HOWES JORDAN ,  MATTHEWS JEANNA ,  WELLS STEVEN ,  HINTON GLENN ,  PINTO OSCAR

IPC: G06F12/08 ,  G06F13/16

公开(公告)号：GB2442162B

公开(公告)日：2010-09-15

申请号：GB0724745

申请日：2006-06-30

Applicant: INTEL CORP

Inventor： TRIKA SANJEEV ,  FABERT ROBERT ,  COULSON RICK ,  MATTHEWS JEANNA

IPC: G06F12/02

Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.

公开(公告)号：GB2473149B

公开(公告)日：2012-10-17

申请号：GB201015976

申请日：2009-06-09

Applicant: INTEL CORP

Inventor： JUENEMANN DALE J ,  HOWES JORDAN ,  MATTHEWS JEANNA ,  WELLS STEVEN ,  HINTON GLENN ,  PINTO OSCAR P ,  TETRICK RAYMOND SCOTT

IPC: G06F12/08 ,  G06F13/16

Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

公开(公告)号：GB2442162A

公开(公告)日：2008-03-26

申请号：GB0724745

申请日：2006-06-30

Applicant: INTEL CORP

Inventor： TRIKA SANJEEV ,  FABERT ROBERT ,  COULSON RICK ,  MATTHEWS JEANNA

IPC: G06F12/02

Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occured last.

公开(公告)号：GB2473149A

公开(公告)日：2011-03-02

申请号：GB201015976

申请日：2009-06-09

Applicant: INTEL CORP

Inventor： JUENEMANN DALE J ,  HOWES JORDAN ,  MATTHEWS JEANNA ,  WELLS STEVEN ,  HINTON GLENN ,  PINTO OSCAR P ,  TETRICK RAYMOND SCOTT

IPC: G06F12/08 ,  G06F13/16

Abstract: In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.