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公开(公告)号：NO317739B1
公开(公告)日：2004-12-13
申请号：NO980873
申请日：1998-02-27
Applicant: INTEL CORP
Inventor： FISHER STEPHEN A , BUI TUAN H , PELEG ALEXANDER D , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF , LIN CHU DERRICK , BINDAL AHMET
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公开(公告)号：DE19581873C2
公开(公告)日：1999-04-15
申请号：DE19581873
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
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公开(公告)号：HK1003189A1
公开(公告)日：1998-10-16
申请号：HK98102178
申请日：1998-03-16
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
Abstract: A processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
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公开(公告)号：NO980873L
公开(公告)日：1998-04-28
申请号：NO980873
申请日：1998-02-27
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER D , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF , LIN CHU DERRICK , BINDAL AHMET
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公开(公告)号：BR9509841A
公开(公告)日：1997-11-25
申请号：BR9509841
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILIND , MENNEMEIER LARRY M , EITAN BENNY
Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
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Patent Agency Ranking
公开(公告)号：AU4595596A
公开(公告)日：1996-06-19
申请号：AU4595596
申请日：1995-12-01
Applicant: INTEL CORP
Inventor： PELEG ALEXANDER , YAARI YAAKOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY
Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
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公开(公告)号：DE19681660C2
公开(公告)日：2000-11-02
申请号：DE19681660
申请日：1996-12-17
Applicant: INTEL CORP
Inventor： GLEW ANDREW , VAKKALAGADDA RAMAMOHAN R , LIN DERRICK , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI EIICHI , EITAN BENNY
Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
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公开(公告)号：DE19681660T1
公开(公告)日：1998-10-29
申请号：DE19681660
申请日：1996-12-17
Applicant: INTEL CORP
Inventor： GLEW ANDREW , VAKKALAGADDA RAMAMOHAN R , LIN DERRICK , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI EIICHI , EITAN BENNY
Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
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公开(公告)号：AU1468297A
公开(公告)日：1997-07-17
申请号：AU1468297
申请日：1996-12-24
Applicant: INTEL CORP
Inventor： DULONG CAROLE , MENNEMEIER LARRY M , PELEG ALEXANDER D , BUI TUAN H , KOWASHI EIICHI , MITTAL MILLIND , EITAN BENNY , FISHER STEPHEN A , MAYTAL BENNY
Abstract: A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.
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公开(公告)号：AU1426397A
公开(公告)日：1997-07-17
申请号：AU1426397
申请日：1996-12-18
Applicant: INTEL CORP
Inventor： MENNEMEIER LARRY M , PELEG ALEXANDER D , GOTTLIEB KOBY
Abstract: In a computer system storing a first packed data and a second packed data having corresponding data elements where the data elements representing unsigned values having a system for determining the absolute difference of the corresponding data elements. The system comprising the steps of subtracting with saturation the data elements in the first packed data from the corresponding data elements in the second packed data to generate a third packed data in response to a first instruction, subtracting with saturation the data elements in the second packed data from the corresponding data elements in the first packed data to generate a fourth packed data in response to a second instruction and performing an operation to select the data elements of the third packed data and the fourth packed data of greatest value to generate a fifth packed data in response to a third instruction.
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