公开(公告)号：AU2011305091A1

公开(公告)日：2013-03-14

申请号：AU2011305091

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/06 ,  G06F9/30

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：SG11201704300TA

公开(公告)日：2017-07-28

申请号：SG11201704300T

申请日：2015-11-24

Applicant: INTEL CORP

Inventor： OULD-AHMED-VALL ELMOUSTAPHA ,  HUGHES CHRISTOPHER J ,  VALENTINE ROBERT ,  GIRKAR MILIND B ,  IDO HIDEKI ,  WU YOUFENG ,  WANG CHENG

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a hardware decoder to decode an instruction, the instruction to include an opcode and an operand to store a portion of a fallback address, execution hardware to execute the decoded instruction to initiate a data speculative execution (DSX) region by activating DSX tracking hardware to track speculative memory accesses and detect ordering violations in the DSX region, and storing the fallback address.

公开(公告)号：AU2013387185B2

公开(公告)日：2016-08-04

申请号：AU2013387185

申请日：2013-05-30

Applicant: INTEL CORP

Inventor： RONG HONGBO ,  WANG CHENG ,  PARK HYUNCHUL ,  WU YOUFENG

IPC: G06F12/00

Abstract: Abstract of the Disclosure In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register 5 assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other 10 embodiments are described and claimed. 2095201vl

公开(公告)号：AU2013387185A1

公开(公告)日：2014-12-18

申请号：AU2013387185

申请日：2013-05-30

Applicant: INTEL CORP

Inventor： RONG HONGBO ,  WANG CHENG ,  PARK HYUNCHUL ,  WU YOUFENG

IPC: G06F12/00

Abstract: Abstract of the Disclosure In an embodiment, a system includes a processor including one or more cores and a plurality of alias registers to store memory range information associated with a plurality of operations of a loop. The memory range information references one or more memory locations within a memory. The system also includes register 5 assignment means for assigning each of the alias registers to a corresponding operation of the loop, where the assignments are made according to a rotation schedule, and one of the alias registers is assigned to a first operation in a first iteration of the loop and to a second operation in a subsequent iteration of the loop. The system also includes the memory coupled to the processor. Other 10 embodiments are described and claimed. 2095201vl

公开(公告)号：AU2011305091B2

公开(公告)日：2014-09-25

申请号：AU2011305091

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： WANG CHENG ,  LIU WEI ,  BORIN EDSON ,  BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  HU SHILIANG

IPC: G06F9/06 ,  G06F9/30

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：SG188993A1

公开(公告)日：2013-05-31

申请号：SG2013018742

申请日：2011-09-26

Applicant: INTEL CORP

Inventor： BRETERNITZ JR MAURICIO ,  WU YOUFENG ,  WANG CHENG ,  BORIN EDSON ,  HU SHILIANG ,  ZILLES CRAIG B

Abstract: An apparatus and method is described herein for conditionally committing /andor speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.