公开(公告)号：US10122420B2

公开(公告)日：2018-11-06

申请号：US14979185

申请日：2015-12-22

Applicant: Intel IP Corporation

Inventor： Thorsten Meyer ,  Andreas Augustin ,  Reinhard Golly ,  Peter Baumgartner

IPC: H04B5/00 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065

Abstract: Apparatus and methods are provided for wireless communications between integrated circuits or integrated circuit dies of an electronic system. In an example, an apparatus can include a first integrated circuit die including a plurality of integrated circuit devices, a second integrated circuit die including a second plurality of integrated circuit devices, and a conductor device configured to wirelessly receive a signal from the first integrated circuit die, to conduct the signal from a first end of an electrical conductor of the conductor device to a second end of the electrical conductor, and to wirelessly transmit the signal to the second integrated circuit die from the second end of the electrical conductor.

公开(公告)号：US20170345678A1

公开(公告)日：2017-11-30

申请号：US15590890

申请日：2017-05-09

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

公开(公告)号：US09543224B1

公开(公告)日：2017-01-10

申请号：US14964494

申请日：2015-12-09

Applicant: INTEL IP CORPORATION

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Robert L. Sankman

IPC: H01L23/48 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L21/60

CPC classification number: H01L22/20 ,  H01L21/4853 ,  H01L21/568 ,  H01L22/12 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L24/76 ,  H01L24/96 ,  H01L24/97 ,  H01L2021/60292 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1421 ,  H01L2924/18162

Abstract: Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include encapsulating a semiconductor die with a molding compound, applying a seed layer on the die and the molding compound, applying a resist layer on the seed layer, exposing a first portion of the resist layer, and exposing a second portion of the resist layer. The first portion can include a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL. The second portion can include the second area of the resist layer that includes the electrical communications pathway.

Abstract translation: 描述了形成这种封装的半导体封装和方法，系统和装置。 形成半导体封装的方法可以包括用模塑料包封半导体管芯，在晶粒上施加种子层和模塑料，在种子层上施加抗蚀剂层，暴露抗蚀剂层的第一部分，并暴露 抗蚀剂层的第二部分。 第一部分可以包括用于形成再分布层（RDL）的抗蚀剂层的第一区域，而不包括用于在至少一个接触焊盘和至少一个接触焊盘之间形成电通信路径的抗蚀剂层的第二区域 RDL。 第二部分可以包括包括电通信路径的抗蚀剂层的第二区域。

公开(公告)号：US20160013153A1

公开(公告)日：2016-01-14

申请号：US14329717

申请日：2014-07-11

Applicant: Intel IP Corporation

Inventor： Thorsten Meyer

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/568 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/8203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/15311

Abstract: An apparatus includes at least a first IC die and a second IC die. Bottom surfaces of the first and second IC dice include a first plurality of connection pads and top surfaces of the first and second IC dice include a second plurality of connection pads. The apparatus also includes a layer of non-conductive material covering the top surfaces of the first and second IC dice, a plurality of through-vias, first conductive interconnect between at least a portion of the first plurality of connection pads and at least one through via, and second conductive interconnect on a top surface of the layer of non-conductive material that provides electrical continuity between at least a portion of the second plurality of connection pads and at least one through-via of the plurality of through-vias.

Abstract translation: 一种装置至少包括第一IC芯片和第二IC芯片。 第一和第二IC芯片的底表面包括第一多个连接焊盘，第一和第二IC芯片的顶表面包括第二多个连接焊盘。 该装置还包括覆盖第一和第二IC芯片的顶表面的非导电材料层，多个通孔，第一多个连接焊盘的至少一部分和至少一个通孔之间的第一导电互连 通孔和第二导电互连，其在非导电材料层的顶表面上提供第二多个连接焊盘的至少一部分与多个通孔中的至少一个通孔之间的电连续性。

公开(公告)号：US10903166B2

公开(公告)日：2021-01-26

申请号：US16060918

申请日：2016-01-28

Applicant: Sanka Ganesan ,  Thorsten Meyer ,  Gerald Ofner ,  Intel IP Corporation

Inventor： Sanka Ganesan ,  Thorsten Meyer ,  Gerald Ofner

IPC: H01L29/40 ,  H01L23/532 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: Disclosed herein are integrated circuit (IC) packages, and related structures and techniques. In some embodiments, an IC package may include: a die; a redistribution structure, wherein the die is coupled to the redistribution structure via first-level interconnects and solder; a solder resist; and second-level interconnects coupled to the redistribution structure through openings in the solder resist.

公开(公告)号：US10301176B2

公开(公告)日：2019-05-28

申请号：US15857461

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81B7/00 ,  B81C1/00

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US10228725B2

公开(公告)日：2019-03-12

申请号：US15282633

申请日：2016-09-30

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner

IPC: A44C5/00 ,  A44C5/02 ,  A44C5/10 ,  A45F5/00 ,  A61B5/00 ,  A61B5/11 ,  G06F1/16 ,  A61B5/021 ,  A61B5/024 ,  G04B37/14 ,  G04B47/00 ,  A61B5/0205 ,  H04B1/3827

Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.