公开(公告)号：US10403609B2

公开(公告)日：2019-09-03

申请号：US15776475

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Sven Albers ,  Georg Seidemann ,  Andreas Wolter ,  Klaus Reingruber ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/02 ,  H01L25/16 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.

公开(公告)号：US20170284636A1

公开(公告)日：2017-10-05

申请号：US15087477

申请日：2016-03-31

Applicant: Intel IP Corporation

Inventor： Marc Stephan Dittes ,  Sven Albers ,  Christian Georg Geissler ,  Andreas Wolter ,  Klaus Reingruber ,  Georg Seidemann ,  Thomas Wagner ,  Richard Patten

IPC: F21V11/00 ,  F21V23/00 ,  H01L33/58 ,  H01L33/54 ,  H01L33/48 ,  H01L33/62

CPC classification number: H01L25/167 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/73257 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.

公开(公告)号：US20170162314A1

公开(公告)日：2017-06-08

申请号：US14956859

申请日：2015-12-02

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter

IPC: H01F27/28 ,  H01F27/24

CPC classification number: H01F27/2804 ,  H01F27/06 ,  H01F27/24 ,  H01F2027/065 ,  H01F2027/2809

Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.

公开(公告)号：US09397019B2

公开(公告)日：2016-07-19

申请号：US14189938

申请日：2014-02-25

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装，其包括具有与第一侧相对设置的第一侧和第二侧的管芯。 IC封装还可以包括封装模具的至少一部分并且具有与模具的第一侧相邻的第一表面的封装材料和与第一表面相对设置的第二表面。 在实施例中，第二表面可以被成形为使得IC封装的一个或多个横截面积比IC封装的一个或多个其它横截面积更薄。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10854590B2

公开(公告)日：2020-12-01

申请号：US15776378

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Richard Patten ,  Georg Seidemann ,  Christian Geissler

IPC: H01L23/02 ,  H01L25/00 ,  H01L25/065 ,  H05K1/11

Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

公开(公告)号：US10228725B2

公开(公告)日：2019-03-12

申请号：US15282633

申请日：2016-09-30

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner

IPC: A44C5/00 ,  A44C5/02 ,  A44C5/10 ,  A45F5/00 ,  A61B5/00 ,  A61B5/11 ,  G06F1/16 ,  A61B5/021 ,  A61B5/024 ,  G04B37/14 ,  G04B47/00 ,  A61B5/0205 ,  H04B1/3827

Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

公开(公告)号：US20170170111A1

公开(公告)日：2017-06-15

申请号：US14970355

申请日：2015-12-15

Applicant: Intel IP Corporation

Inventor： Klaus Jürgen REINGRUBER ,  Sven Albers ,  Christian Georg Geissler ,  Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/528 ,  H01L23/00 ,  H05K1/11 ,  C25D5/54 ,  C25D7/12 ,  C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  H01L23/522 ,  H05K1/02

CPC classification number: H01L23/528 ,  C25D5/022 ,  C25D5/10 ,  C25D5/48 ,  C25D5/54 ,  C25D7/123 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/10253 ,  H01L2924/14 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

公开(公告)号：US10741486B2

公开(公告)日：2020-08-11

申请号：US15062143

申请日：2016-03-06

Applicant: Intel IP Corporation

Inventor： Klaus Reingruber ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H05K1/16 ,  H01L23/538 ,  H01L23/31 ,  H01L23/522

Abstract: Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.

公开(公告)号：US10672731B2

公开(公告)日：2020-06-02

申请号：US15776051

申请日：2015-12-23

Applicant: Intel IP Corporation

Inventor： Sven Albers ,  Klaus Reingruber ,  Georg Seidemann ,  Christian Geissler ,  Richard Patten

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/433 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

公开(公告)号：US10553538B2

公开(公告)日：2020-02-04

申请号：US16152221

申请日：2018-10-04

Applicant: Intel IP Corporation

Inventor： Klaus Jürgen Reingruber ,  Sven Albers ,  Christian Georg Geissler ,  Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00 ,  C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  C25D5/54 ,  C25D7/12 ,  H01L23/522 ,  H05K1/02 ,  H05K1/11

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.