公开(公告)号：US20190393130A1

公开(公告)日：2019-12-26

申请号：US16018268

申请日：2018-06-26

Applicant: Intel IP Corporation

Inventor： Reinhard Mahnkopf ,  Sonja Koller ,  Andreas Wolter

IPC: H01L23/373 ,  H01L27/12 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498 ,  H01L21/768

Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.

公开(公告)号：US09397019B2

公开(公告)日：2016-07-19

申请号：US14189938

申请日：2014-02-25

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装，其包括具有与第一侧相对设置的第一侧和第二侧的管芯。 IC封装还可以包括封装模具的至少一部分并且具有与模具的第一侧相邻的第一表面的封装材料和与第一表面相对设置的第二表面。 在实施例中，第二表面可以被成形为使得IC封装的一个或多个横截面积比IC封装的一个或多个其它横截面积更薄。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11037855B2

公开(公告)日：2021-06-15

申请号：US16467582

申请日：2016-12-30

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Reinhard Mahnkopf

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/10

Abstract: A system-in-package apparatus includes a contoured heat sink that provides a first recess and a subsequent recess. The system-in-package apparatus includes a flexible printed wiring board that is wrapped onto the contoured heat sink after a manner to enclose the first semiconductive device into the first recess and a semiconductive device in the subsequent recess.

公开(公告)号：US10347558B2

公开(公告)日：2019-07-09

申请号：US15748475

申请日：2015-08-31

Applicant: INTEL IP CORPORATION

Inventor： Christian Geissler ,  Georg Seidemann ,  Sonja Koller ,  Jan Proschwitz

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/367 ,  H01L25/04 ,  H01L25/07 ,  H01L23/13 ,  H01L23/36 ,  H01L23/42 ,  H01L21/56 ,  H01L23/498

Abstract: Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.

公开(公告)号：US20190206777A1

公开(公告)日：2019-07-04

申请号：US15857207

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Lizabeth Keser ,  Bernd Waidhas ,  Georg Seidmann

IPC: H01L23/498 ,  H01L21/48 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H05K3/4007 ,  H05K2201/095 ,  H05K2201/10378

Abstract: An interposer for an electronic package including at least one angled via. The interposer can include a dielectric layer including a first surface and a second surface. The dielectric layer can include a normal axis perpendicular with the first or second surface. In an example, an angled via can include a first end located along the first surface and a second end located along the second surface. A longitudinal axis of the angled via can be extended between the first end and the second end. The longitudinal axis is disposed at an angle from the normal axis to form an angled via.

公开(公告)号：US20190103333A1

公开(公告)日：2019-04-04

申请号：US15719653

申请日：2017-09-29

Applicant: Intel IP Corporation

Inventor： Reinhard Mahnkopf ,  Andreas Wolter ,  Sonja Koller

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L27/02 ,  H01L27/12 ,  H01L21/48 ,  H01L21/762

Abstract: A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.

公开(公告)号：US11410908B2

公开(公告)日：2022-08-09

申请号：US16018268

申请日：2018-06-26

Applicant: Intel IP Corporation

Inventor： Reinhard Mahnkopf ,  Sonja Koller ,  Andreas Wolter

IPC: H01L23/373 ,  H01L27/12 ,  H01L23/367 ,  H01L23/498 ,  H01L21/768 ,  H01L23/00

Abstract: Present disclosure relates to IC devices with thermal mitigation structures in the form of metal structures provided in a semiconductor material of a substrate on which active electronic devices are integrated (i.e., front-end metal structures). In one aspect, an IC device includes a substrate having a first face and a second face, where at least one active electronic device is integrated at the first face of the substrate. The IC device further includes at least one front-end metal structure that extends from the first face of the substrate into the substrate to a depth that is smaller than a distance between the first face and the second face. Providing front-end metal structures may enable improved cooling options because such structures may be placed in closer vicinity to the active electronic devices, compared to conventional thermal mitigation approaches.

公开(公告)号：US20200227388A1

公开(公告)日：2020-07-16

申请号：US16641241

申请日：2017-09-29

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Thomas Wagner ,  Andreas Wolter ,  Andreas Augustin ,  Sonja Koller ,  Thomas Ort ,  Reinhard Mahnkopf

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor die, a semiconductor device comprising a second semiconductor die, and one or more wire bond structures. The wire bond structure includes a bond interface portion. The wire bond structure is arranged next to the first semiconductor die. The first semiconductor die and the bond interface portion of the wire bond structure are arranged at the same side of the semiconductor device. An interface contact structure of the semiconductor device is electrically connected to the wire bond structure.

公开(公告)号：US10658201B2

公开(公告)日：2020-05-19

申请号：US15935128

申请日：2018-03-26

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498

Abstract: A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.

公开(公告)号：US20190207027A1

公开(公告)日：2019-07-04

申请号：US16298680

申请日：2019-03-11

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Sonja Koller ,  Georg Seidemann

IPC: H01L29/78 ,  H01L23/50 ,  H01L23/00 ,  H01L29/66 ,  H01L23/498

CPC classification number: H01L29/7835 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L29/66659

Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.