公开(公告)号：WO2013082378A3

公开(公告)日：2013-08-22

申请号：PCT/US2012067221

申请日：2012-11-30

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/44

CPC classification number: G06F13/24 ,  H03M1/06 ,  H03M1/1225 ,  H03M1/164 ,  H03M1/44

Abstract: An early interrupt feature enables generation of interrupts prior to completion of an analog-to-digital conversion to be used in a processor PID calculation. Even though an analog-to-digital conversion is still in process, the PID application software can use the early interrupt time to begin execution of an interrupt service routine (ISR). The early interrupt can improve the throughput and response time of the PID control loop by overlapping the completion of the ADC conversion with the processor overhead associated with the interrupt request. A plurality of pipelined registers, each having substantially the same delay time as the pipelined stages of the ADC, are selectable to provided a delay time that may be used to generate an early interrupt, wherein the latency time between an ADC conversion and processing of an interrupt relating to that ADC conversion may thereby be shortened.

Abstract translation: 早期中断功能可以在完成模数转换之前产生中断，以在处理器PID计算中使​​用。 即使模数转换仍在进行中，PID应用软件可以使用早期中断时间来开始执行中断服务程序（ISR）。 早期中断可以通过将ADC转换的完成与与中断请求相关联的处理器开销重叠来提高PID控制环路的吞吐量和响应时间。 可以选择多个流水线寄存器，每个流水线寄存器具有与ADC的流水线阶段基本上相同的延迟时间，以提供可用于产生早期中断的延迟时间，其中ADC转换和处理 因此可以缩短与该ADC转换有关的中断。

公开(公告)号：WO2013048727A3

公开(公告)日：2013-05-23

申请号：PCT/US2012054734

申请日：2012-09-12

Applicant: MICROCHIP TECH INC ,  KRIS BRYAN

Inventor： KRIS BRYAN

IPC: H03K7/08 ,  H02M3/156 ,  H03K19/003

CPC classification number: H03K7/08 ,  H02M3/1584 ,  H03K19/00315 ,  H04L25/4902

Abstract: Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events, PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle.

Abstract translation: 生成多相，频率相干脉宽调制（PWM）信号，无论用户或系统事件如何，均可维持PWM数据集的一致性，通过在数据中添加数据缓冲器来保存和传输新的PWM数据来实现PWM数据集的一致性 从处理器设置更新。 在数据传输到数据缓冲区完成之后，当下一个PWM周期即将开始时，数据缓冲器中存储的数据组将及时传送到有源PWM寄存器，以便下一个PWM周期的开始。

公开(公告)号：WO2007050738A3

公开(公告)日：2008-01-31

申请号：PCT/US2006041751

申请日：2006-10-25

Applicant: MICROCHIP TECH INC ,  KRIS BRYAN

Inventor： KRIS BRYAN

IPC: G06F1/26

CPC classification number: H02J1/14 ,  G06F1/26 ,  H02J13/0003 ,  Y02B90/228 ,  Y04S20/18

Abstract: A plurality of power supply modules having their outputs coupled in parallel are controlled for load balancing purposes through a digital communications channel. The digital communications channel may be a wired digital serial or parallel bus, and/or a wireless digital communications channel such as Bluetooth, infrared, etc. Each of the plurality of power supply modules may broadcast their respective output currents and all of the plurality of power supply modules may determine a total current supplied to a load and thereby determine an appropriate output voltage for proportionally contributing to the total current.

Abstract translation: 通过数字通信信道来控制具有并联耦合的多个电源模块用于负载平衡目的。 数字通信信道可以是有线数字串行或并行总线，和/或诸如蓝牙，红外等的无线数字通信信道。多个电源模块中的每一个可以广播它们各自的输出电流，并且所有多个 电源模块可以确定提供给负载的总电流，从而确定适当的输出电压以对总电流进行比例的贡献。

公开(公告)号：WO2016149086A3

公开(公告)日：2016-11-03

申请号：PCT/US2016021977

申请日：2016-03-11

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  WOJEWODA IGOR ,  CATHERWOOD MIKE ,  FALL BRIAN ,  TOLLEFSON JASON ,  PEPPING JIM ,  MICKEY DAVE ,  SPOHRER THOMAS ,  DUMAIS ALEX ,  WILKIE CALUM ,  SHEARD VINCENT

IPC: G06F15/167 ,  G06F1/22 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F1/22 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/167 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins. a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract translation: 微控制器装置具有带有多个外部引脚的外壳。 具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一系统总线耦合的第一存储器以及与第一系统总线耦合的第一多个外围设备，以及第二微控制器 与第二中央处理单元（CPU），与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器以及与第二系统总线耦合的第二多个外围设备，其中第一与第二微控制器仅通信 通过专用接口。

公开(公告)号：WO2016149078A3

公开(公告)日：2016-11-03

申请号：PCT/US2016021962

申请日：2016-03-11

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  WOJEWODA IGOR ,  CATHERWOOD MIKE ,  FALL BRIAN ,  TOLLEFSON JASON ,  WILKIE CALUM ,  MICKEY DAVE ,  SPOHRER THOMAS ,  DUMAIS ALEX

IPC: G06F15/78 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data bus width of the first and second microcontroller.

Abstract translation: 微控制器装置具有壳体，多个外部引脚具有多个输入/输出引脚，具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一中央处理单元 系统总线和与第一系统总线耦合的第一多个外围设备，具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器，以及 与第二系统总线耦合的第二多个外围设备，以及焊盘所有权复用器单元，其可控制以将输入/输出引脚的控制分配给第一微控制器或第二微控制器，其中外部引脚的数量小于 第一和第二微控制器的数据总线宽度之和。

公开(公告)号：WO2014133768A3

公开(公告)日：2014-10-23

申请号：PCT/US2014016189

申请日：2014-02-13

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  DAY JOHN ,  DUMAIS ALEX ,  BOWLING STEPHEN

IPC: H02M1/32 ,  H02M1/08 ,  H02M1/38 ,  H02M3/335

CPC classification number: H03K5/133 ,  H02M1/08 ,  H02M1/32 ,  H02M1/38 ,  H02M3/3353 ,  H02M3/33576

Abstract: A plurality of PWM generators have user configurable time delay circuits for each PWM control signal generated therefrom. The time delay circuits are adjusted so that each of the PWM control signals arrive at their associated power transistors at the same time. This may be accomplished by determining a maximum delay time of the PWM control signal that has to traverse the longest propagation time and then setting the delay for that PWM control signal to substantially zero delay. Thereafter, all other delay time settings for the other PWM control signals may be determined by subtracting the propagation time for each of the other PWM control signals from the longest propagation time. Thereby insuring that all of the PWM control signals arrive at their respective power transistor control nodes with substantially the same time relationships as when they left their respective PWM generators.

Abstract translation: 多个PWM发生器具有用于由其产生的每个PWM控制信号的用户可配置时间延迟电路。 延时电路被调整，使得每个PWM控制信号同时到达它们相关的功率晶体管。 这可以通过确定必须经过最长传播时间的PWM控制信号的最大延迟时间，然后将该PWM控制信号的延迟设置为基本为零延迟来实现。 此后，可以通过从最长传播时间中减去每个其他PWM控制信号的传播时间来确定用于其他PWM控制信号的所有其他延迟时间设置。 由此确保所有PWM控制信号以与它们离开它们各自的PWM发生器时基本相同的时间关系到达它们各自的功率晶体管控制节点。

公开(公告)号：WO2013048820A3

公开(公告)日：2013-07-04

申请号：PCT/US2012055897

申请日：2012-09-18

Applicant: MICROCHIP TECH INC ,  KRIS BRYAN

Inventor： KRIS BRYAN

IPC: H03K7/08 ,  G06F1/04

CPC classification number: H03K7/08 ,  G06F1/04 ,  G06F1/26

Abstract: Groups of phase shifted PWM signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

Abstract translation: 生成相移PWM信号组，以保持其占空比和相位关系作为PWM信号频率周期的函数。 多相PWM信号以比例度量方式生成，以大大简化和减少PWM系统中使用的处理器的计算工作量。 相移PWM信号的组也可以与外部同步信号同步并自动缩放以匹配外部同步信号。

公开(公告)号：WO2014164631A3

公开(公告)日：2014-11-27

申请号：PCT/US2014023049

申请日：2014-03-11

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  REITER ANDREAS ,  FUTO TIBOR ,  DUMAIS ALEX

IPC: H02M3/157 ,  H02M3/335

CPC classification number: H03M1/66 ,  H02M3/157 ,  H02M3/33515 ,  H03M3/502 ,  H03M7/3028 ,  H03M7/3042

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. This slope compensation function may be provided by a digital slope compensation generator and a pulse density modulated digital-to- analog converter (PDM DAC) having a selectable response mode low pass filter.

Abstract translation: 斜率补偿模块使用电流模式控制提供开关模式电源的斜率补偿。 该斜率补偿函数可以由数字斜率补偿生成器和具有可选响应模式低通滤波器的脉冲密度调制数模转换器（PDM DAC）提供。

公开(公告)号：WO2013048816A3

公开(公告)日：2013-07-11

申请号：PCT/US2012055885

申请日：2012-09-18

Applicant: MICROCHIP TECH INC ,  KRIS BRYAN

Inventor： KRIS BRYAN

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A plurality of pulse width modulation (PWM) generators are provided, each having a separate phase offset counter to create a phase shift instead of using either a time base counter preload value or an adder to create the phase shift offset relative to the PWM time base and the duty cycle. The phase shifting process is separated from the duty cycle generation process, thereby easing the task of preserving the duty cycle and phase relationships among the various PWM channels following an asynchronous external synchronization event. At least one master time base generates a PWM cycle start signal that resets the phase offset counters in each of the PWM generator circuits. The phase offset counter continues counting until it matches the respective phase offset value. At that time, the associated duty cycle counter is reset and restarted. The duty cycle continues until its count matches the specified duty cycle value at which time the duty cycle counter stops until reset by the terminal count from the phase offset counter. The output of the duty cycle comparators provide the output PWM signals as a repetitive series of single cycle PWM signals.

Abstract translation: 提供了多个脉宽调制（PWM）发生器，每个发生器具有单独的相位偏移计数器以产生相移而不是使用时基计数器预载值或加法器来创建相对于PWM时基的相移偏移 和工作周期。 相移过程与占空比生成过程分离，从而简化了在异步外部同步事件之后保持各种PWM通道之间的占空比和相位关系的任务。 至少有一个主时基产生一个PWM周期启动信号，用于复位每个PWM发生器电路中的相位偏移计数器。 相位偏移计数器继续计数，直到它与相应的相位偏移值相匹配。 此时，相关的占空比计数器复位并重新启动。 占空比一直持续到其计数与指定的占空比值相匹配，此时占空比计数器停止，直到由相位偏移计数器的终端计数器复位。 占空比比较器的输出将输出PWM信号作为重复的一系列单周期PWM信号。

公开(公告)号：WO2013048817A3

公开(公告)日：2013-07-04

申请号：PCT/US2012055891

申请日：2012-09-18

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN

IPC: H03K7/08 ,  G06F1/04

CPC classification number: H03K7/08 ,  G06F1/04

Abstract: A "quasi-master-time-base" circuit is used to periodically resynchronize the individual PWM generators to a know reference signal. This quasi-master-time-base will be at the lowest frequency relative to all of the PWM output frequencies, wherein all of the PWM output frequencies are at the same frequency or at an integer multiple frequency(ies) of the quasi-master frequency. This "quasi-master-time-base" circuit allows for minor timing errors due to user PWM configuration errors and/or update errors, and still yields stable PWM signal outputs that remain synchronized to each other.

Abstract translation: “准主时基”电路用于周期性地将各个PWM发生器重新同步到已知的参考信号。 该准主时基将处于相对于所有PWM输出频率的最低频率，其中，所有PWM输出频率都处于准主频率的相同频率或整数倍频率（ies） 。 该“准主时基”电路允许由于用户PWM配置错误和/或更新错误引起的较小时序错误，并且仍然产生稳定的PWM信号输出，这些输出保持彼此同步。