公开(公告)号：AT222657T

公开(公告)日：2002-09-15

申请号：AT98117770

申请日：1998-09-18

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: An instruction set for a microcontroller which has robust multiple word instructions. The instruction set has a plurality of instructions wherein the plurality of instructions comprises single word instructions and multiple word instructions. At least one bit is located in a predetermined location in all non-first words of all multiple word instructions. The bit will be decoded by the microcontroller as no operation bit if the first word of the multiple word instruction is not executed prior to execution of any succeeding words in the multiple word instruction.

公开(公告)号：ES2165651T3

公开(公告)日：2002-03-16

申请号：ES98119390

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：DE69801355D1

公开(公告)日：2001-09-20

申请号：DE69801355

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：DE602007011105D1

公开(公告)日：2011-01-20

申请号：DE602007011105

申请日：2007-12-12

Applicant: MICROCHIP TECH INC

Inventor： PESAVENTO RODNEY J ,  LAHTI GREGG D ,  TRIECE JOSEPH W

IPC: G06F12/08

公开(公告)号：DE69807412T2

公开(公告)日：2003-04-17

申请号：DE69807412

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W ,  MITRA SUMIT K

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

Abstract: A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

公开(公告)号：AU2002323646A1

公开(公告)日：2003-04-01

申请号：AU2002323646

申请日：2002-09-09

Applicant: MICROCHIP TECH INC

Inventor： PHOENIX TIMOTHY J ,  TRIECE JOSEPH W

IPC: G06F9/445 ,  G06F12/06

公开(公告)号：AT221682T

公开(公告)日：2002-08-15

申请号：AT00107116

申请日：2000-04-07

Applicant: MICROCHIP TECH INC

Inventor： BOLES EDWARD BRIAN ,  DRAKE RODNEY J ,  TRIECE JOSEPH W

IPC: G06F15/78 ,  G06F9/50 ,  G06F13/40

公开(公告)号：DE69804562D1

公开(公告)日：2002-05-08

申请号：DE69804562

申请日：1998-09-28

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

公开(公告)号：AT215713T

公开(公告)日：2002-04-15

申请号：AT98118314

申请日：1998-09-28

Applicant: MICROCHIP TECH INC

Inventor： MITRA SUMIT K ,  TRIECE JOSEPH W

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/35 ,  G06F9/355

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

公开(公告)号：AT545089T

公开(公告)日：2012-02-15

申请号：AT07865699

申请日：2007-12-14

Applicant: MICROCHIP TECH INC

Inventor： TRIECE JOSEPH W ,  PESAVENTO RODNEY J ,  LAHTI GREGG D ,  DAWSON STEVEN

IPC: G06F13/30 ,  G06F1/32 ,  G06F13/28

Abstract: A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.