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公开(公告)号：CA2053862A1
公开(公告)日：1991-01-22
申请号：CA2053862
申请日：1990-06-21
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY W , TAHERNIA OMID
Abstract: 2053862 9102410 PCTABS00003 An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider (4), second divider (5), synchronization circuit (6) for providing a first modulus control signal (7) to the dual modulus divider (4), and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal (1) is in a first state.
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公开(公告)号：CA2053907A1
公开(公告)日：1991-01-15
申请号：CA2053907
申请日：1990-06-04
Applicant: MOTOROLA INC
Inventor： TAHERNIA OMID , HEROLD BARRY W , BURCH KENNETH R
IPC: H03B5/32
Abstract: A dual bandwidth crystal controlled oscillator is described having a first transconductance amplifier providing sufficient gain to maintain oscillation with an oscillator crystal at a minimum current drain. A second transconductance amplifier is provided which can be selectively coupled to the first transconductance amplifier, thereby augmenting the gain of the first transconductance amplifier to provide the capability for rapid oscillator start-up following battery saver operation. The dual bandwidth crystal controlled oscillator can be utilized in conventional oscillator and frequency synthesizer applications.
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公开(公告)号：CA2046294A1
公开(公告)日：1990-09-14
申请号：CA2046294
申请日：1990-02-23
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY W , TAHERNIA OMID
Abstract: 2046294 9010978 PCTABS00002 A frequency synthesizer (10) governed by a battery saving signal (20) having sleep and awake cycles (60, 62) comprises a phase locked loop and a control circuit (70) for enhancing the restart operation of the phase locked loop at the commencement of each awake cycle of the battery saving signal. More specifically, the phase locked loop includes a phase detector (26, 28) for locking the frequencies generated by a reference oscillator (12) and a voltage controlled oscillator (36) by adjusting a signal (38) in a storage device (34) used for governing the voltage controlled oscillator. During the sleep and awake cycles of the battery saving signal, the oscillators and phase detector are inhibited and enabled, respectively, in their operations. The control circuit is operative to inhibit the adjustment of the governing signal until both of the oscillators are determined to be effectively enabled at the commencement of each awake cycle of the battery saving signal to ensure the stored governing signal commences at its desired setting.
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公开(公告)号：SG45258A1
公开(公告)日：1998-01-16
申请号：SG1996002158
申请日：1988-06-16
Applicant: MOTOROLA INC
Inventor： BENNETT PAUL T , WILLARD DAVID F , TAHERNIA OMID , PAGE JAMES C , SPIRO ALLAN I , LAMBRECHT FRANK E
Abstract: A paging receiver device (10) and method are disclosed in which analog information transmitted from an external source such as a paging transmitter are received and decoded. The analog information includes at least one voice message. The voice message is recovered, digitized, and stored in one of a plurality of message slots in a memory (50) of the paging receiver (10). In response to a paging user's request, the digitized stored message is recalled from memory (50), reconverted from digital information to analog information, and used to produce audible voice information being a replica of the original analog voice message.
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公开(公告)号：DE69028113T2
公开(公告)日：1997-03-06
申请号：DE69028113
申请日：1990-05-18
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY , TAHERNIA OMID , DAVIS WALTER , RIVAS MARIO
Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.
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Patent Agency Ranking
公开(公告)号：IN177272B
公开(公告)日：1996-12-21
申请号：IN418DE1990
申请日：1990-05-03
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY WAYNE , TAHERNIA OMID , DAVIS WALTER LEE , RIVAS MARIO ALBERTO
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公开(公告)号：DE69026259T2
公开(公告)日：1996-10-02
申请号：DE69026259
申请日：1990-06-21
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY , TAHERNIA OMID
Abstract: An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.
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公开(公告)号：AT141452T
公开(公告)日：1996-08-15
申请号：AT90917819
申请日：1990-05-18
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY WAYNE , TAHERNIA OMID , DAVIS WALTER LEE , RIVAS MARIO ALBERTO
Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.
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公开(公告)号：AT136178T
公开(公告)日：1996-04-15
申请号：AT90911029
申请日：1990-06-21
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY WAYNE , TAHERNIA OMID
Abstract: An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.
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公开(公告)号：CA2050901C
公开(公告)日：1995-03-21
申请号：CA2050901
申请日：1990-05-18
Applicant: MOTOROLA INC
Inventor： HEROLD BARRY W , TAHERNIA OMID , DAVIS WALTER L , RIVAS MARIO A
Abstract: A frequency synthesizer (fig. 1), which has at least one programmably characterized phase lock loop circuit (10,14) includes a buffer memory (40,fig.4) and an interface controller (38,fig.2) responsive to operational codes received from a central controller (12) to direct transfer of data words (50,52) for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.
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