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    23.
    发明专利
    未知

    公开(公告)号：IT1246238B

    公开(公告)日：1994-11-17

    申请号：IT8360490

    申请日：1990-02-16

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: H03K3/354 ,  H02M3/07 ,  H03B

    Abstract: A voltage-boosted phase oscillator for driving a voltage multiplier comprises two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from the normal phase through a bootstrap circuit. The frequency of oscillation of both intermeshed ring oscillators is established by means of two similar RC networks common to both loops. The synchronization of the respective oscillations of the two rings is ensured by means of a plurality of SR flip-flops connected in cascade, formed by two NAND gates which, singularly, constitute as many inverters of the two rings. The oscillation and the arresting of the oscillation are controlled by means of a logic signal fed to a common input of a first pair of NAND gates which constitute respectively a first inverter of the relative ring oscillator and to a second input of which the phase produced by the relative ring oscillator is fed.

    24.
    发明专利
    未知

    公开(公告)号：DE69012382D1

    公开(公告)日：1994-10-20

    申请号：DE69012382

    申请日：1990-03-12

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： OLIVO MARCO ,  RIVA CARLO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    Abstract: A reference cell for reading EEPROM memory devices, capable of discharging any charges present in its own floating gate (3) without varying the geometry of the cell with respect to that of the associated memory cells and without requiring specific manufacturing steps. For this purpose, a switch element, for example a diode (D1), is provided between the floating gate (3) and the substrate (11) of the device and discharges any charges present in the floating gate toward the substrate during the cell idle state (in the absence of read signals)

    27.
    发明专利
    未知

    公开(公告)号：ITVA910022D0

    公开(公告)日：1991-07-31

    申请号：ITVA910022

    申请日：1991-07-31

    Applicant: ST MICROELECTRONICS SRL ,  SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/417 ,  G11C7/10 ,  G11C7/14 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413

    Abstract: Spurious memory readings which may be caused by noise induced by transitions in the output buffers of a fast parallel memory device are prevented by permitting output latches to change state in function of newly extracted data signals by means of an enabling pulse having a preestablished duration and which is generated only after a change of memory address signals has occurred and the new configuration of memory address signals has lasted for a time which is not shorter than the time of propagation of signals through the memory chain. The enabling pulse is generated by employing a detector of transitions occurring in the input circuitry of the memory, a dummy memory chain, a one-shot pulse generator and a resetting pulse generator. The anti-noise network may be exploited also for implementing an auto-stand-by condition at the end of each read cycle, which reduces power consumption and increases speed by implifying the sensing process.

    29.
    发明专利
    未知

    公开(公告)号：DE69220632T2

    公开(公告)日：1998-01-02

    申请号：DE69220632

    申请日：1992-08-27

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G06F1/24 ,  H03K17/00 ,  H03K17/22

    Abstract: A power-on reset circuit utilizes capacitive couplings and does not establish any static current path bewteen the supply rails. The circuit has a null static consumption and may be advantageously integrated in CMOS micrologics. Moreover the circuit is insensitive to rebounds on the supply rails and to internal and external noise.

    30.
    发明专利
    未知

    公开(公告)号：DE69115952D1

    公开(公告)日：1996-02-15

    申请号：DE69115952

    申请日：1991-02-07

    Applicant: SGS THOMSON MICROELECTRONICS

    Inventor： PASCUCCI LUIGI ,  OLIVO MARCO

    IPC: G11C11/419 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18

    Abstract: A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCCmax. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

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