公开(公告)号：DE69226004D1

公开(公告)日：1998-07-30

申请号：DE69226004

申请日：1992-07-17

Applicant: CONS RIC MICROELETTRONICA ,  ST MICROELECTRONICS SRL

Inventor： ZISA MICHELE ,  BELLUSO MASSIMILIANO ,  PAPARO MARIO

IPC: H03K4/58 ,  H03K5/02 ,  H03K17/06 ,  H03F3/217 ,  H03K17/687 ,  H03K19/017

Abstract: In a bootstrap circuit for a power MOS transistor in the high driver configuration, comprising a first capacitor (C1) chargeable to a first voltage function of the supply voltage of the power transistor (T1), there is present a second capacitor (C2) combined with the first capacitor (C1) in such a way as to make available a second voltage higher than the first voltage and the threshold voltage of the power transistor (T1).

公开(公告)号：DE69128936D1

公开(公告)日：1998-03-26

申请号：DE69128936

申请日：1991-11-25

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： PAPARO MARIO ,  AIELLO NATALE

IPC: H01L21/8238 ,  H01L21/761 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H02M7/219 ,  H01L21/76

Abstract: The structure comprises at least arms (1, 2) each formed from a first and a second MOS transistor (M3, M1; M4, M2). Its integrated monolithic construction provides for a type N++ substrate (3) forming a positive potential output terminal (K1) which is overlaid by a type N-epitaxial layer (4). For each of the first transistors (M3; M4) this comprises a type P, P+ insulating region (13, 25; 14, 26) containing a type N+ enriched drain region (15; 16), a type N drain region (19; 20) and, in succession, a type P body region (21; 22) and a pair of type N+ source regions (23; 24) forming a negative potential output terminal (A1) respectively. For each of the second transistors (M1, M2) the structure comprises a type N+ enriched drain region (5, 6) containing a type N drain region (31, 32) and in succession a type P body region (9; 10) and a pair of type N+ regions (11; 12) forming corresponding alternating current inputs (A3, A4) respectively.

公开(公告)号：DE69022262T2

公开(公告)日：1996-05-15

申请号：DE69022262

申请日：1990-02-12

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PAPARO MARIO ,  PALARA SERGIO

IPC: H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H03K5/02 ,  H01L21/76 ,  H01L27/02

Abstract: The monolithic integrated structure comprises a semiconductor substrate (1), a superimposed first epitaxial stratum (2) having characteristics such as to withstand a high supply voltage applied to the driving system and a first and a second insulation pocket (3, 4) which may be connected to a high voltage and to ground, respectively, and diffused in said first epitaxial stratum (2) at a distance such as to define an interposed area (25) of said first stratum (2) capable of insulating said insulating pockets (3, 4) from one another. Within the latter pockets (3, 4), there are provided respective embedded strata (6, 7) and superimposed regions (8, 9) of a second epitaxial stratum having characterstics such as to withstand the low voltage applied across the two driving stages. A further region (5) of said second epitaxial stratum is superimposed over said area (25) of said first epitaxial stratum (2). The above regions (8, 9) of insulation pockets (3, 4) are designed for the formation of two high and low voltage driving stages (DR1, DR2), while the above further region (5) of the second epitaxial stratum may be used for the formation of a level translator circuit component (T3). Means (20, 21; 22, 23) are provided for the protection of said circuit component (T3) against high supply voltages.

公开(公告)号：IT8922289A1

公开(公告)日：1991-05-07

申请号：IT2228989

申请日：1989-11-07

Applicant: SGS THOMSON MICROELECTRONICS S R L

Inventor： PALARA SERGIO ,  PAPARO MARIO

IPC: H01L20060101 ,  H01L21/822 ,  H01L29/74 ,  H01L27/02 ,  H01L27/04

公开(公告)号：DE69032552T2

公开(公告)日：1999-02-25

申请号：DE69032552

申请日：1990-10-18

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PALARA SERGIO ,  PAPARO MARIO ,  PELLICANO' ROBERTO

IPC: G05F1/56 ,  G05F1/10 ,  G05F3/22 ,  H01F7/18 ,  H03K17/16 ,  H03K17/615

Abstract: The limiting circuit comprises a comparator (B), which makes the comparison between the output voltage (Vc) of the power device (T5, T6) and a predetermined reference voltage (Vrif). In the case wherein the output voltage (Vc) is just below the reference voltage (Vrif) the comparator (B) supplies a current to the load (L) suitable for preventing the output voltage from falling further below said reference voltage (Vrif).

公开(公告)号：DE69022262D1

公开(公告)日：1995-10-19

申请号：DE69022262

申请日：1990-02-12

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PAPARO MARIO ,  PALARA SERGIO

IPC: H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H03K5/02 ,  H01L21/76 ,  H01L27/02

Abstract: The monolithic integrated structure comprises a semiconductor substrate (1), a superimposed first epitaxial stratum (2) having characteristics such as to withstand a high supply voltage applied to the driving system and a first and a second insulation pocket (3, 4) which may be connected to a high voltage and to ground, respectively, and diffused in said first epitaxial stratum (2) at a distance such as to define an interposed area (25) of said first stratum (2) capable of insulating said insulating pockets (3, 4) from one another. Within the latter pockets (3, 4), there are provided respective embedded strata (6, 7) and superimposed regions (8, 9) of a second epitaxial stratum having characterstics such as to withstand the low voltage applied across the two driving stages. A further region (5) of said second epitaxial stratum is superimposed over said area (25) of said first epitaxial stratum (2). The above regions (8, 9) of insulation pockets (3, 4) are designed for the formation of two high and low voltage driving stages (DR1, DR2), while the above further region (5) of the second epitaxial stratum may be used for the formation of a level translator circuit component (T3). Means (20, 21; 22, 23) are provided for the protection of said circuit component (T3) against high supply voltages.

公开(公告)号：IT1236667B

公开(公告)日：1993-03-25

申请号：IT2228989

申请日：1989-11-07

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PAPARO MARIO ,  PALARA SERGIO

IPC: H01L21/822 ,  H01L29/74 ,  H01L27/02 ,  H01L27/04 ,  H01L

Abstract: The device accomplishes the protection against breakdown of an N+ type diffuse region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises an N+ type substrate (1) over which there is superimposed an N- type epitaxlal layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffuse region (6). The diffuse region (6) is insulated electrically with respect to the A type containment region (5).

公开(公告)号：IT1228900B

公开(公告)日：1991-07-09

申请号：IT1957089

申请日：1989-02-27

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PAPARO MARIO ,  PALARA SERGIO

IPC: H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/06 ,  H03K5/02 ,  H01L

Abstract: The monolithic integrated structure comprises a semiconductor substrate (1), a superimposed first epitaxial stratum (2) having characteristics such as to withstand a high supply voltage applied to the driving system and a first and a second insulation pocket (3, 4) which may be connected to a high voltage and to ground, respectively, and diffused in said first epitaxial stratum (2) at a distance such as to define an interposed area (25) of said first stratum (2) capable of insulating said insulating pockets (3, 4) from one another. Within the latter pockets (3, 4), there are provided respective embedded strata (6, 7) and superimposed regions (8, 9) of a second epitaxial stratum having characterstics such as to withstand the low voltage applied across the two driving stages. A further region (5) of said second epitaxial stratum is superimposed over said area (25) of said first epitaxial stratum (2). The above regions (8, 9) of insulation pockets (3, 4) are designed for the formation of two high and low voltage driving stages (DR1, DR2), while the above further region (5) of the second epitaxial stratum may be used for the formation of a level translator circuit component (T3). Means (20, 21; 22, 23) are provided for the protection of said circuit component (T3) against high supply voltages.

公开(公告)号：IT8922289D0

公开(公告)日：1989-11-07

申请号：IT2228989

申请日：1989-11-07

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PAPARO MARIO ,  PALARA SERGIO

IPC: H01L21/822 ,  H01L29/74 ,  H01L27/02 ,  H01L27/04 ,  H01L

Abstract: The device accomplishes the protection against breakdown of an N+ type diffuse region (6) inserted in a vertical-type semiconductor integrated power structure. Such a structure comprises an N+ type substrate (1) over which there is superimposed an N- type epitaxlal layer (2) in which a grounded P type insulation pocket (3) is obtained. The insulation pocket (3) contains an N type region (4) including a P type region (5) for the containment of the N+ type diffuse region (6). The diffuse region (6) is insulated electrically with respect to the A type containment region (5).

公开(公告)号：DE3869656D1

公开(公告)日：1992-05-07

申请号：DE3869656

申请日：1988-05-13

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： PALARA SERGIO ,  PERNICIARO SPATRISANO ANTONIO ,  PAPARO MARIO ,  GIACALONE PIETRO

IPC: H01L23/28 ,  H01L21/56 ,  H01L23/495 ,  H01L23/52 ,  H01L25/04 ,  H01L25/07 ,  H01L25/18

Abstract: The circuit comprises several metal plates (A,B,C) onto each of which a chip (D,E,F) is soldered, the chips being connected together and to their respective rheophores (1,2.....9) by means of bonding wires. The plates and the other internal electrical components are reciprocally insulated by means of the resin which constitutes the encapsulation.