公开(公告)号：JP2001358092A

公开(公告)日：2001-12-26

申请号：JP2000176216

申请日：2000-06-13

Applicant: SONY CORP

Inventor： KOMAI HISANORI ,  NOGAMI TAKESHI ,  KITO HIDEYOSHI ,  TAGUCHI MITSURU

IPC: C25D5/48 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To eliminate large steps on a wafer (substrate) due to a plated seed layer at a part that is not in contact with electrolytic polishing liquid that remains for connecting an electrode and was a subject when introducing the electrolytic polishing method into a wafer process. SOLUTION: This method for manufacturing a semiconductor device is provided with a process for forming a plated seed layer 22 on a substrate 11, a process for forming a plated film 23 on the plated seed layer 22 excluding a part on the outer-periphery part of the substrate 11 by the plating method, a process for polishing the plated film 23 along with the plated seed layer 22 by electrolytic polishing, and a process for selectively removing the plated film 23 remaining on the outer-periphery part of the substrate 11.

公开(公告)号：JP2001044191A

公开(公告)日：2001-02-16

申请号：JP21150199

申请日：1999-07-27

Applicant: SONY CORP

Inventor： IKEDA KOICHI ,  FUKAZAWA MASANAGA ,  KITO HIDEYOSHI ,  HASEGAWA TOSHIAKI

IPC: H01L21/302 ,  C08J7/00 ,  C08J7/04 ,  C08K3/04 ,  C08L83/04 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device, such as signal propagation delay, by reducing capacitance between interconnect layers and capacitance between interconnects while forming a silicon oxide film containing carbon on an organic insulating film. SOLUTION: A silicon oxide film 12 containing carbon is formed on an organic insulating film 11. Due to carbon present therein, the film 12 exhibits low relative permittivity while still holding the inorganic properties of a conventional silicon oxide film not containing an impurity such as carbon. Therefore, even when the insulating film having inorganic properties is formed on the film 11 having a low relative permittivity, lower relative permittivity can be achieved. Thus, a laminated insulating film 13 is interposed between interconnect layers and between interconnects, whereby capacitance between the interconnect layers and between the interconnects can be reduced, and this contributes to improving the performance of a semiconductor device, such as signal propagation delay.

公开(公告)号：JP2008281727A

公开(公告)日：2008-11-20

申请号：JP2007125217

申请日：2007-05-10

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KITO HIDEYOSHI

IPC: G02F1/1333

Abstract: PROBLEM TO BE SOLVED: To provide a liquid crystal panel of high image quality, wherein a uniform cell gap can be obtained even when no spacer is in a display area.
SOLUTION: In the liquid crystal panel, a prescribed gap is constituted by sticking a pair of substrates 10 and 20 by using a sealing material 30 and a liquid crystal 40 is encapsulated in the gap between the substrates 10 and 20. A film 21 is formed on the surface on the outer side of the reflection side substrate 20 in the liquid crystal panel. The film 21 can apply prescribed stress to the reflection side substrate 20. Curvature of the substrate 20 is corrected by the stress applied to the substrate 20 from the film 21 and unevenness of the gap between the substrates 10 and 20 is suppressed.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种高图像质量的液晶面板，其中即使在显示区域中没有间隔物的情况下也可以获得均匀的单元间隙。 解决方案：在液晶面板中，通过使用密封材料30粘贴一对基板10和20而构成规定的间隙，并且将液晶40封装在基板10和20之间的间隙中。膜 21形成在液晶面板的反射侧基板20的外侧的表面上。 膜21可以向反射侧基板20施加规定的应力。通过从膜21施加到基板20的应力校正基板20的曲率，并抑制基板10和20之间的间隙的不均匀。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2002305193A

公开(公告)日：2002-10-18

申请号：JP2001107505

申请日：2001-04-05

Applicant: SONY CORP

Inventor： KITO HIDEYOSHI ,  HASEGAWA TOSHIAKI

IPC: C23C16/42 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To solve the problems of deterioration in the characteristics or peeling occurs in an insulating film or metal wiring in a semiconductor device having an insulating film structure, in which a silicon oxide film and an organic insulating film are laminated, etc. SOLUTION: This semiconductor device has an insulation layer, obtained by laminating a first insulating film 1, made of a silicon oxide film and a second insulating film 2 made of an organic insulating film. The silicon oxide film is that subjected to moisture absorption suppression, which has a characteristic that a ratio SI/SII of area integrals SI and SII of degas spectra is between 1 and 1.5 inclusive by ion current measurement in temperature-programmed desorption mass spectrometry, based on masses 18 of the laminated layer structure of the silicon oxide film and the organic insulating film and a single-layer structure of a silicon oxide film.

公开(公告)号：JP2002076000A

公开(公告)日：2002-03-15

申请号：JP2000267901

申请日：2000-09-05

Applicant: SONY CORP

Inventor： TAGUCHI MITSURU ,  NOGAMI TAKESHI ,  KITO HIDEYOSHI ,  KOMAI HISANORI

IPC: C25D7/12 ,  C25F3/16 ,  C25F3/22 ,  C25F3/30 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To conformally and stably grow and form a copper seed layer by electroplating to improve about the film peel off or copper burying failures. SOLUTION: The method comprises a step of forming a barrier layer in recesses (connecting holes 17 and trenches 18) formed in a substrate, a step of forming an oxidation preventing layer 22 on the surface of a barrier layer 21 without exposing the barrier layer 21 surface to an oxidative atmosphere after forming the barrier layer 21, a step of removing the oxidation preventing layer 22 by electrolytic polishing, and a step of forming a plating seed layer 23 on the barrier layer 21 surface by electroplating following the electrolytic polishing.

公开(公告)号：JP2001338926A

公开(公告)日：2001-12-07

申请号：JP2000157542

申请日：2000-05-29

Applicant: SONY CORP

Inventor： KOMAI HISANORI ,  NOGAMI TAKESHI ,  KITO HIDEYOSHI ,  TAGUCHI MITSURU ,  ANDO KATSUMI

IPC: H01L21/3205 ,  C23F1/18 ,  H01L21/304 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H05K3/42

Abstract: PROBLEM TO BE SOLVED: To realize electrolytic polishing in the state where excessive polishing and unpolished remainder do not occur due to the local step produced in a material to be polished, and to introduce the electrolytic polishing into a semiconductor manufacturing process. SOLUTION: This method comprises a step of forming a wiring material film 16 that buries a recessed part 13 formed in an insulating film 12 on the insulating film 12 formed on the substrate 11 by a plating method, a step of relaxing the local step S produced on a surface of the wiring material film 16 while keeping the state that the wiring material film 16 is left on the insulating film 12, and a step of removing the wiring material film 16 on the insulating film 12 by the electrolytic polishing so as to leave the wiring material film 16 only in a groove 13.

公开(公告)号：JP2001077196A

公开(公告)日：2001-03-23

申请号：JP25376999

申请日：1999-09-08

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  IKEDA KOICHI ,  KITO HIDEYOSHI

IPC: H01L21/32 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing by using a structure of a mask in which the recycling of a resist film is enabled and using a material having a low permittivity in the lowermost layer of the mask when a wiring structure is formed on an interlayer dielectric including a low organic film having a low permittivity. SOLUTION: This semiconductor device comprises the step of forming a 3-layer mask of different materials consisting of a first mask 24, a second mask 22, and a third mask 21 from the bottom layer on an interlayer dielectric 12 including first and second low dielectric constant films 13, 15. The second mask 22 is formed with a film of a material that protects a first film 16 which forms the first mask 24 when the third mask 21 is formed, and the first film 16 is formed with a low permittivity material.

公开(公告)号：JP2001077192A

公开(公告)日：2001-03-23

申请号：JP24543999

申请日：1999-08-31

Applicant: SONY CORP

Inventor： KITO HIDEYOSHI

IPC: H01L23/522 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device, which has a Cu anti-diffusion layer having a relative dielectric constant of about 6 or smaller and having a satisfactory alignment with a wiring step and/or an etching stopper layer, and also to provide a method for manufacturing a semiconductor device. SOLUTION: In the semiconductor device, a P-SiN film 12 having a composition ratio Si/N of 0.75 or less or an P-SiON film is as a Cu anti-diffusion film and/or an etching stopper layer. A non-SiN-based insulating film, such as a P-SiO film having N-H groups on its surface generated by an HMDS process may be uses as the CU anti-diffusion layer and/or etching stopper layer.

公开(公告)号：JP2001023924A

公开(公告)日：2001-01-26

申请号：JP19527299

申请日：1999-07-09

Applicant: SONY CORP

Inventor： MIYATA KOJI ,  MIYAMOTO TAKAAKI ,  KITO HIDEYOSHI

IPC: H01L21/768 ,  H01L21/28

Abstract: PROBLEM TO BE SOLVED: To obtain the forming method of a plug, which can suppress the contact resistance low between a wiring and the plug, even when the wiring is a borderless wiring and moreover, there is lithographic deviation of the plug from the wiring, and forming method of the plug. SOLUTION: This method is formation method of a plug, which is provided with a process of forming a via hole 8, which leads to a wiring 4 in an interlayer insulating film 5 covering the wiring 4, a process of selectively etching one part, which is exposed in the via hole 8, of the wiring 4 to deepen the via hole 8 (8a) and a process of embeddin a conductive material 11 in the via hole 8a to form the plug 14. The film 5 can consist of a hygroscopic material.

公开(公告)号：JP2000195855A

公开(公告)日：2000-07-14

申请号：JP36897898

申请日：1998-12-25

Applicant: SONY CORP

Inventor： KITO HIDEYOSHI

IPC: H01L21/768 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To remove only the space formation material from silicon inorganic material through selection of baking temperature by using an organic compound polymer for the space forming material, and forming an inorganic porous insulating film, using silicon inorganic material where it is added. SOLUTION: An interlayer insulating film 12 consisting of silicon oxide or the like is made on a semiconductor substrate 11. A semiconductor element is made on the semiconductor substrate 11, and aluminum metallic wiring is made within the interlayer insulating film 12. Next, an inorganic porous insulating film 13 is made, using the silicon inorganic material where space formation material to form space with the film is added, on the interlayer insulating film 12 of a substrate 10 by rotational coating method. For the space forming material, for example, low-density polyethylene is used as a polymer which has thermal decomposition temperature higher than the temperature, at which the silicon inorganic material causes bridging reaction and lower than the baking temperature of the silicon inorganic material.