公开(公告)号：DE602004010226D1

公开(公告)日：2008-01-03

申请号：DE602004010226

申请日：2004-02-20

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTALDO ENRICO ,  CONTE ANTONINO ,  TORRISI SALVATORE ,  SAMBATARO VINCENZO

IPC: G06F1/26 ,  G11C16/30

公开(公告)号：DE60304311T2

公开(公告)日：2006-12-21

申请号：DE60304311

申请日：2003-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  CASTALDO ENRICO

IPC: H02M3/07

Abstract: The circuit has a voltage comparator (400) to compare a charge pump output voltage and a reference voltage. A clock control (425) conditions a charge pump clocking based on the comparison result. The comparator has a sampling unit for sampling the charge pump output voltage at a sampling rate. A frequency divider (415) and frequency selection state machine (410) controls the sampling rate based on voltage comparison result. Independent claims are also included for the following: (a) an integrated circuit including a charge pump voltage generator and a charge pump regulator circuit (b) a method of regulating an output voltage of a charge-pump voltage generator.

公开(公告)号：DE60304311D1

公开(公告)日：2006-05-18

申请号：DE60304311

申请日：2003-06-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  CASTALDO ENRICO

IPC: H02M3/07

Abstract: The circuit has a voltage comparator (400) to compare a charge pump output voltage and a reference voltage. A clock control (425) conditions a charge pump clocking based on the comparison result. The comparator has a sampling unit for sampling the charge pump output voltage at a sampling rate. A frequency divider (415) and frequency selection state machine (410) controls the sampling rate based on voltage comparison result. Independent claims are also included for the following: (a) an integrated circuit including a charge pump voltage generator and a charge pump regulator circuit (b) a method of regulating an output voltage of a charge-pump voltage generator.

公开(公告)号：ITVA20020020D0

公开(公告)日：2002-03-04

申请号：ITVA20020020

申请日：2002-03-04

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTALDO ENRICO ,  CONTE ANTONINO

IPC: H02M3/07

Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal. A phase generator circuit has an input for receiving the timing signal from the logic control circuit for generating control phases for the charge pump.

公开(公告)号：ITRM20010282D0

公开(公告)日：2001-05-24

申请号：ITRM20010282

申请日：2001-05-24

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  CONCEPITO ORESTE

IPC: G11C16/24 ,  G11C16/28

Abstract: A reading circuit for a memory includes a current detector for each bit line of the memory, a reference voltage generator, and a comparator that compares the reference voltage with the voltage of a reading terminal of the current detector. Each current detector includes a first transistor whose gate is selectively connected to the reading terminal, and whose drain-source path is in series with a respective bit line. An input of a first inverter stage is connected to the source of the first transistor, and an output thereof is connected to the gate of the first transistor. The circuit has a very short reading time based upon each of the current detectors including a first resistor between the source of the first transistor and the bit line, along with second and third transistors having their drain-source paths connected in series with the respective bit line, and along with second and third inverters connected to the respective bit line. First and second resistive elements are also connected between the first and second transistors and the respective bit line.

公开(公告)号：ITMI992149D0

公开(公告)日：1999-10-14

申请号：ITMI992149

申请日：1999-10-14

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  GAIBOTTI MAURIZIO ,  ZERILLI TOSSAMO

IPC: G11C7/06 ,  G11C7/14

Abstract: A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.

公开(公告)号：IT201800003622A1

公开(公告)日：2019-09-15

申请号：IT201800003622

申请日：2018-03-15

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  MARINO LEOPOLDO MARIA ,  PERRONI MAURIZIO FRANCESCO ,  POLIZZI SALVATORE

IPC: G11C20060101

公开(公告)号：ITMI20120310A1

公开(公告)日：2013-08-30

申请号：ITMI20120310

申请日：2012-02-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  LOGIUDICE GIANBATTISTA ,  UCCIARDELLO CARMELO

公开(公告)号：ITMI20110306A1

公开(公告)日：2012-08-29

申请号：ITMI20110306

申请日：2011-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTE ANTONINO ,  DI MARTINO ALBERTO JOSE ,  GIAQUINTA MARIA ,  MATRANGA GIOVANNI

公开(公告)号：DE602006009091D1

公开(公告)日：2009-10-22

申请号：DE602006009091

申请日：2006-07-06

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTALDO ENRICO ,  CONTE ANTONINO ,  LO GIUDICE GIANBATTISTA

IPC: G11C5/14 ,  H02M3/07

Abstract: There is disclosed an integrated control circuit (3) for a charge pump (1). The integrated circuit comprises a first device (112,N1,N2,R,12) suitable for regulating the output voltage (Vout) of the charge pump (1) and a second device (113,M10,M11,C11,11) suitable for increasing the output voltage (Vout) from the charge pump with a set ramp. The integrated circuit comprises means (111) suitable for activating said first device and providing it with a first value of a supply signal (Ireg) in a first period of time (A) and suitable for activating said second device and for providing it with a second value (Iramp) of the supply signal that is greater than the first value in a second period of time (C) after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value (Vlow) to a second value (Vhigh) that is greater than the first value, said second value being fixed by the reactivation of the first device.