公开(公告)号：FR2837023B1

公开(公告)日：2004-05-28

申请号：FR0202853

申请日：2002-03-06

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  GENDRIER PHILIPPE ,  FOURNEL RICHARD

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

公开(公告)号：FR2823363B1

公开(公告)日：2003-12-12

申请号：FR0104621

申请日：2001-04-05

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  CASPAR DANIEL

IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/14

Abstract: A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.

公开(公告)号：FR2838554A1

公开(公告)日：2003-10-17

申请号：FR0209454

申请日：2002-07-25

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  GENDRIER PHILIPPE

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/02

Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

公开(公告)号：FR2829279A1

公开(公告)日：2003-03-07

申请号：FR0111381

申请日：2001-09-03

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  CASPAR DANIEL ,  FOURNEL RICHARD

IPC: G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

公开(公告)号：FR2817413B1

公开(公告)日：2003-02-28

申请号：FR0015447

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  THOMAS SIGRID

IPC: G11C5/14 ,  G11C8/08 ,  G11C16/04 ,  G11C16/30 ,  H03K19/003 ,  H03K17/0412 ,  H03K17/56

Abstract: A high voltage switching device includes a switching circuit for switching a high voltage to an output line and for providing a control signal. The high voltage switching device also includes a switching transistor connected to the switching circuit for switching a low voltage to the output line based upon the control signal. The output signal is controlled by a control circuit that sets up a control loop between the drop in the gate voltage level of the switching transistor and the voltage level of the output line that is controlled by the switching circuit.

公开(公告)号：FR2823363A1

公开(公告)日：2002-10-11

申请号：FR0104621

申请日：2001-04-05

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  DRAY CYRILLE ,  CASPAR DANIEL

IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/14

Abstract: The method is for electrical erasing of a memory cell (CM) of type FAMOS, which comprises a p-MOS transistor with a floating gate which is not connected. The erasing is by the application of determined voltages to the bulk (B), the source (S) and the drain (D) of the transistor by an erasing module (MEF), that is a voltage VB to the bulk, which is higher than at last 4-6 V, with still lower voltages VS and VD applied to the source and the drain, respectively, and below a limiting voltage which causes the destruction of the cell, which is about 10 V. The difference between voltages applied to the source and the drain is non-null and positive, and below a predetermined threshold, which is about 1 V. For example, in the case of 0.18 micrometer technology, the source voltage is about 1 V, the drain voltage null, and the bulk voltage about 7-8 V, and the erasing takes about 1 minute. The difference between the source and the drain voltages is variable in the course of erasing process. The memory device comprises an electrically erasable memory cell (CM) of type FAMOS. The p-MOS transistor of the memory cell has a standard linear configuration, or more advantageously a ring ocnfiguration which comprises a central electrode surrounded by the gate and a peripheral electrode. The device comprises programming means for writing data into the memory cell, reading means for reading the content of the memory cell, and control means for selectively connecting the means for programming, reading and erasing of the memory cell. The device comprises several electrically erasable memory cells of type FAMOS. The memory device is a part of an integrated circuit.

公开(公告)号：FR2817413A1

公开(公告)日：2002-05-31

申请号：FR0015447

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  THOMAS SIGRID

IPC: G11C5/14 ,  G11C8/08 ,  G11C16/04 ,  G11C16/30 ,  H03K19/003 ,  H03K17/0412 ,  H03K17/56

Abstract: The switching device comprises a voltage-shift type switching circuit for switching a higher supply voltage (HV) on at least one output line (L1) of capacitve type, a transistor (M30) for switching a lower supply voltage Vcc(V1) on the same output line, and a control circuit (4) for controlling the drop of the gate voltage of the switching transistor (M30) from the higher supply voltage to the ground potential subjected to the drop of the output line voltage from the higher supply voltage in the lower supply voltage. The switchihng circuit comprises two branches; the first branch comprising a loading transistor (M10) connected to the higher supply voltage terminal (HV), a switching transistor (M13) connected to the ground and receiving as the gate voltage the inverse of control voltage (CTRL), one or more cascade transistors (M11,M12) connected between the two transistors, and a repeater transistor (M40) connected in series in the same branch and associated with the output line by the intermediary of node (N11) providing the gate signal to the lower supply voltage switching transistor (M30) directly connected to the output line; the second branch comprises a set of transistors starting with a loading transistor (M20); and a transistor (M50) is connected as a resistor between the two branches for favouring the polarization of the cascade transistors. The voltage-shift circuit (40) applies a biasing voltage (Vbias2) as the gate voltage to the repeater transistor (M40) of the first branch of the switching circuit. The circuit (40) comprises two branches; the first branch comprises a transistor (M41) with the gate and the drain connected together to a polarization node providing the first biasing voltage (Vbias1) and a transistor (M42) connected as a diode; the second branch comprises a transistor (M43) connected as a current mirror with the transistor (M41) of the first branch, and a set of transistors (M44,M45) connected as diodes between the transistor (M43) and the output line. The lower supply voltage (V1) is equal to the logic supply voltage (Vcr). In the second embodiment, the switching device comprises a supplementary loading transistor connected between the higher supply voltage terminal and the output line, and is controlled by the same signal as the loading transistor of the first branch of the switching circuit. The integrated circuit comprises the switching device associated with at least one current-conducting output line. The integrated circuit of a read-only memory store has output lines which are the lines for selecting memory cells. The memory store is of type FAMOS or FLASH-EPROM, and the selection lines are for rows of memory cells.

公开(公告)号：DE60330130D1

公开(公告)日：2009-12-31

申请号：DE60330130

申请日：2003-01-31

Applicant: ST MICROELECTRONICS SA

Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

公开(公告)号：AT449424T

公开(公告)日：2009-12-15

申请号：AT03709915

申请日：2003-01-31

Applicant: ST MICROELECTRONICS SA

Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

公开(公告)号：DE602006006646D1

公开(公告)日：2009-06-18

申请号：DE602006006646

申请日：2006-12-22

Applicant: ST MICROELECTRONICS SA

Inventor： DRAY CYRILLE ,  JACQUET FRANCOIS ,  BARASINSKI SEBASTIEN

IPC: G11C11/419