公开(公告)号：FR3093830B1

公开(公告)日：2021-03-12

申请号：FR1902455

申请日：2019-03-11

Applicant: ST MICROELECTRONICS ROUSSET ,  ST MICROELECTRONICS SA

Inventor： FERRAND OLIVIER ,  OLSON DANIEL ,  BEN SAID ANIS ,  ARDICHVILI EMMANUEL

IPC: G06F13/366 ,  G06F13/42 ,  G06F21/85

Abstract: Le procédé de gestion d’accès à un bus (7a, 7b) partagé par des interfaces (5a, 5b), comprend un déclenchement, lorsque l’accès audit bus est accordé à une des interfaces (5a, 5b), d’un comptage ayant une durée minimale de comptage (DM1, DM2), etune libération de l’accès accordé à l’une des interfaces (5a, 5b)) et une création d’un point d’arbitrage (PA) à l’issue de la durée minimale (DM1, DM2) si au moins une demande d’accès audit bus (7a, 7b) émanant d’au moins une autre des interfaces (5a, 5b) est reçue pendant la durée minimale de comptage (DM1, DM2). Référence : figure 2

公开(公告)号：FR2857111B1

公开(公告)日：2005-10-07

申请号：FR0308053

申请日：2003-07-02

Applicant: ST MICROELECTRONICS SA

Inventor： FERRAND OLIVIER ,  DAVIDESCU DRAGOS

IPC: G06F1/24 ,  G06F11/00 ,  H03K19/00

Abstract: The microcontroller has a reset circuit (3) that selectively generates a reset signal for resetting a microprocessor (2). A detection device (4) has an input (5) for receiving a critical logic signal from the microprocessor. The detection device has an output that applies a reset command on the reset circuit, upon detecting a change in the logic state of the logic signal.

公开(公告)号：FR2867874A1

公开(公告)日：2005-09-23

申请号：FR0402929

申请日：2004-03-22

Applicant: ST MICROELECTRONICS SA

Inventor： FERRAND OLIVIER ,  GRIL MAFFRE JEAN MICHEL

IPC: G06F9/30 ,  G06F9/318 ,  G06F15/00

Abstract: The microprocessor has a mode register (30) with a determined number N of mode bits. A decoding device (28) and an execution unit (12) decodes and executes a given instruction (li) according to two execution modes based on values of a determined number (Qi) of mode bits associated to the instruction. The instruction corresponds to the respective distinct operations in the modes, where Qi is a positive whole number. An independent claim is also included for a method to control a microprocessor having a set of determined instructions that are coded on a number of bits in an instruction coding space.

公开(公告)号：FR2816075B1

公开(公告)日：2004-05-28

申请号：FR0013903

申请日：2000-10-30

Applicant: ST MICROELECTRONICS SA

Inventor： GAILHARD BRUNO ,  FERRAND OLIVIER

IPC: H03L7/099 ,  H03L7/199 ,  G06F1/12

Abstract: An integrated circuit includes a generator for providing a clock signal from a reference signal. The generator, which is of the phase-locked loop type, includes a frequency divider and a phase comparator connected together. A reset circuit is connected to the frequency divider and to the phase comparator for providing a reset signal thereto at each leading edge of the reference signal for synchronizing a low-frequency signal with the reference signal.

公开(公告)号：DE60003315T2

公开(公告)日：2004-04-29

申请号：DE60003315

申请日：2000-07-25

Applicant: ST MICROELECTRONICS SA

Inventor： RUAT LUDOVIC ,  FERRAND OLIVIER ,  GAILHARD BRUNO

IPC: G06K17/00 ,  G06K7/00

Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.

公开(公告)号：FR2816134B1

公开(公告)日：2003-12-05

申请号：FR0013901

申请日：2000-10-30

Applicant: ST MICROELECTRONICS SA

Inventor： GAILHARD BRUNO ,  FERRAND OLIVIER

IPC: H03L7/089 ,  H03L7/18 ,  H03L7/091 ,  H03K19/00

Abstract: A generator producing a clock signal whose frequency depends on a control voltage includes a comparator for comparing a period of the clock signal with a desired period, and for providing at least one first control signal based upon the comparison. The generator includes a sampler circuit for sampling the first control signal, and for producing a first sampled control signal. The generator also includes a voltage generator for providing the variable control voltage as a function of the first sampled control signal.

公开(公告)号：FR2816135A1

公开(公告)日：2002-05-03

申请号：FR0013896

申请日：2000-10-30

Applicant: ST MICROELECTRONICS SA

Inventor： GAILHARD BRUNO ,  FERRAND OLIVIER

IPC: H03K3/03 ,  H03L7/099

Abstract: The generator comprises a digital oscillator producing a clock signal (CKHF) on the basis of N logic signals S(1), S(2), ..., S(N) representing a control number of N bits, where N is an integer greater than 1. The oscillator comprises N+1 components C(0), C(1), ..., C(N), where N components C(1), C(2), ..., C(N) of high weight are each affected by the proper weight i in the range from 1 to N, and the component C(0) of low weight delivers the clock signal, which is branched to the input (e) of component C(N). At least one component C(i) of high weight comprises two branches: the first branch with a cell (F) and an interrupter INTC1(i) connected in series, where the interrupter is controlled by the logic signal S(i) so that it is open when the signal is active; the second branch with a number NC(i)=2i+1 or cells (F) and an interrupter INTC2(i) connected in series, where the interrupter is controlled by the same logic signal so that it is closed when the signal is active. The low-weight component C(0) contains an even number of inverters if N is odd, or an odd number of inverters if N is even. Each cell (F) contains an odd number (NF) of inverters connected in series. At least one cell, or all cells, contains an interrupter (INTF) connected in series with the inverts. The oscillator also comprises means for applying a precharge signal to the cells of the two branches of component C(i). The precharge signal is the clock signal, or its inverse; or the input signal of component C(i). The generator also comprises a comparator for comparing the period of clock signal to a desired period and delivering a control number (NR) of N bits, so that the control number increases/decreases when the period of the clock signal is below/above the desired value, otherwise remains constant.