公开(公告)号：DE602006005861D1

公开(公告)日：2009-05-07

申请号：DE602006005861

申请日：2006-04-11

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  POMET ALAIN

IPC: G06F1/00 ,  G06F21/52 ,  G06F21/77 ,  G06F21/79

Abstract: The method involves calculating a current digital signature of read data with the help of a function taking into account an address (A) of the data in a memory. Coherence between the current signature and a signature previously recorded is verified. The recorded signature is stored in a zone of the memory at the same address as the data. Four groups of temporary storage registers are used for storing the data, the address, the signature extracted from the memory and the current signature.

公开(公告)号：FR2824209A1

公开(公告)日：2002-10-31

申请号：FR0105815

申请日：2001-04-30

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVES ,  ROMAIN FABRICE

IPC: G06F7/72 ,  G06F21/55 ,  G09C1/00 ,  H04L9/18 ,  G06K19/07

Abstract: The invention concerns a method for encrypting, with a random quantity (r), a calculation using at least a modular operation (3), the method consisting in multiplying a first modulo (n) by said random quantity, in taking as modulo of the operation, the result (m) of said multiplication and in carrying out a modular reduction of the result of the operation, on the basis of the first modulo (n).

公开(公告)号：DE69900142T2

公开(公告)日：2001-09-27

申请号：DE69900142

申请日：1999-02-17

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE

IPC: G06F7/52 ,  G06F7/72

Abstract: The modular arithmetic processor is integrated into a modular arithmetic coprocessor (4). The circuit performs and operation of the type S = A asterisk B +C, with S and C coded on 2 asterisk Bt bits and A and B coded on Bt bits. A memory (162 or 262) holds an eventual overflow borrow arising from a computation stage to re-inject into a later calculation stage.

公开(公告)号：DE69900142D1

公开(公告)日：2001-07-19

申请号：DE69900142

申请日：1999-02-17

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE

IPC: G06F7/52 ,  G06F7/72

Abstract: The modular arithmetic processor is integrated into a modular arithmetic coprocessor (4). The circuit performs and operation of the type S = A asterisk B +C, with S and C coded on 2 asterisk Bt bits and A and B coded on Bt bits. A memory (162 or 262) holds an eventual overflow borrow arising from a computation stage to re-inject into a later calculation stage.

公开(公告)号：FR2923923B1

公开(公告)日：2009-12-04

申请号：FR0759136

申请日：2007-11-19

Applicant: ST MICROELECTRONICS SA ,  PROTON WORLD INT NV

Inventor： ROMAIN FABRICE ,  MODAVE JEAN LOUIS

IPC: G06F11/16 ,  G06F21/55 ,  G06F21/60

公开(公告)号：DE602004023436D1

公开(公告)日：2009-11-12

申请号：DE602004023436

申请日：2004-03-29

Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS SRL

Inventor： TEGLIA YANNICK ,  ROMAIN FABRICE ,  LIARDET PIERRE-YVAN ,  FRAGNETO PASQUALINA ,  SOZZANI FABIO ,  BERTONI GUIDO

IPC: H04L9/06

Abstract: A processor for executing a Rijndeal algorithm which applies a plurality of encryption rounds to a data block array in order to obtain an array of identical size, each round involving a key block array and a data block substitution table, wherein said processor comprises: a first input register (102) containing an input data block column; an output register (111) containing an output data block column or an intermediate block column; a second input register (101) containing a key block column or the intermediate data blocks; a block substitution element (104) receiving the data one block at a time following the selection (103) thereof in the first register and providing, for each block, a column of blocks; an element (109) applying a cyclic permutation to the substitution circuit column blocks; and an Exclusive-OR combination element (110) combining the permutation circuit column blocks with the content of the second register, the result of said combination being loaded into the output register.

公开(公告)号：DE60207818T2

公开(公告)日：2006-08-24

申请号：DE60207818

申请日：2002-02-06

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  TEGLIA YANNICK

IPC: G09C1/00 ,  H04L9/06

Abstract: A secured method of cryptographic computation to generate output data from input data and from a secret key includes a derived key scheduling step to provide a derived key from the secret key according to a known key scheduling operation. The method also includes a masking step, performed before the derived key scheduling step, to mask the secret key so that the derived scheduled key is different at each implementation of the method. The present method and component can be used in transfer type applications, such as bank type applications.

公开(公告)号：FR2824209B1

公开(公告)日：2003-08-29

申请号：FR0105815

申请日：2001-04-30

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVES ,  ROMAIN FABRICE

IPC: G06F7/72 ,  G06F21/55 ,  G09C1/00 ,  H04L9/18 ,  G06K19/07

Abstract: The invention concerns a method for encrypting, with a random quantity (r), a calculation using at least a modular operation (3), the method consisting in multiplying a first modulo (n) by said random quantity, in taking as modulo of the operation, the result (m) of said multiplication and in carrying out a modular reduction of the result of the operation, on the basis of the first modulo (n).

公开(公告)号：FR2820576B1

公开(公告)日：2003-06-20

申请号：FR0101685

申请日：2001-02-08

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  TEGLIA YANNICK

IPC: G09C1/00 ,  H04L9/06

Abstract: The protected method of cryptographic computation includes N computation rounds successively performed to produce an output data from an input data and a private key. The method also includes a first masking stage to mask the input data, so that each intermediate data used or produced by a computation round is masked, and a second masking stage to mask data manipulated inside each computation round.

公开(公告)号：FR2820577B1

公开(公告)日：2003-06-13

申请号：FR0101684

申请日：2001-02-08

Applicant: ST MICROELECTRONICS SA

Inventor： ROMAIN FABRICE ,  TEGLIA YANNICK

IPC: G09C1/00 ,  H04L9/06 ,  H04L9/08

Abstract: A secured method of cryptographic computation to generate output data from input data and from a secret key includes a derived key scheduling step to provide a derived key from the secret key according to a known key scheduling operation. The method also includes a masking step, performed before the derived key scheduling step, to mask the secret key so that the derived scheduled key is different at each implementation of the method. The present method and component can be used in transfer type applications, such as bank type applications.