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    22.
    发明专利
    未知

    公开(公告)号：ITMI992651D0

    公开(公告)日：1999-12-20

    申请号：ITMI992651

    申请日：1999-12-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  PIO FEDERICO

    IPC: H01L21/8246 ,  H01L27/112

    Abstract: A non-volatile memory device including a plurality of memory cells, each memory cell formed as MOS transistor with a source region, a drain region and a gate having sides formed therewith; and one or more dielectric spacers disposed on the sides of the gate. At least one memory cell is defined in an ON state and at least one memory cell is defined in an OFF state. The memory cells in the ON state comprise drain regions and source regions of the lightly diffused drain (LDD) type, characterized in that the at least one drain region and the at least one source region of the memory cells in the OFF state are formed by one or more high dopant regions. The memory cells in the OFF state consists of layers of silicide on top of one or more active regions defined as the source region, the drain region, and the gate.

    23.
    发明专利
    未知

    公开(公告)号：DE69325809T2

    公开(公告)日：1999-12-09

    申请号：DE69325809

    申请日：1993-11-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO ,  PIO FEDERICO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: A method for supplying negative programming voltages to non-volatile memory cells in a non-volatile memory device provides for charging a capacitor (C;C1-Cn) to a positive high voltage by connecting, through first switching means (TX,TY;TE1-TEn,TF1-TFn), a first plate (A;A1-An) of the capacitor (C;C1-Cn) to a positive high-voltage supply (Vpp) and connecting, through second switching means (TB;TZ;TD1-TDn), a second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn), which is also operatively connected to the control gate of at least one memory cell, to a reference voltage supply (GND), and for successively connecting, through said first switching means (TX,TY;TE1-TEn,TF1-TFn) the first plate (A;A1-An) of the capacitor (C;C1-Cn) to the reference voltage supply (GND) and disconnecting the second plate (B;B';B1-Bn) of the capacitor (C;C1-Cn) from the reference voltage supply (GND) to obtain a negative voltage on said second plate (B;B';B1-Bn) voltage.

    25.
    发明专利
    未知

    公开(公告)号：DE602006009662D1

    公开(公告)日：2009-11-19

    申请号：DE602006009662

    申请日：2006-08-24

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： MICHELONI RINO ,  CRIPPA LUCA ,  RAVASIO ROBERTO ,  PIO FEDERICO

    IPC: G11C16/34

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    27.
    发明专利
    未知

    公开(公告)号：DE60129294D1

    公开(公告)日：2007-08-23

    申请号：DE60129294

    申请日：2001-02-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PIO FEDERICO

    IPC: G11C16/34

    Abstract: Method for refreshing data stored in an electrically erasable and programmable non-volatile semiconductor memory comprising at least one two-dimensional array (1) of memory cells (MC) containing a plurality of individually erasable and programmable memory pages (R). Each time a request to modify a content of a memory page is received by the memory, the method provides for modifying (201;502;602) the content of said memory page and submitting a portion (S1-SZ;R) of the two-dimensional array to a refresh procedure (202-208;501,503-509;601,603-612). The refresh procedure comprises detecting (203;505;606) memory cells of that memory portion that have partially lost a respective datum stored therein and reprogramming the datum in the detected memory cells.

    28.
    发明专利
    未知

    公开(公告)号：DE69734509D1

    公开(公告)日：2005-12-08

    申请号：DE69734509

    申请日：1997-07-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PIO FEDERICO

    IPC: H01L21/8246 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  G11C16/02 ,  H01L29/788 ,  H01L29/792

    Abstract: Array of electrically programmable non-volatile memory cells, each cell comprising a floating gate (9;90), a control gate (12;120) coupled to a row (WL) of the array, a first electrode (7,13;70;130) associated with a column (BL1-BL8) of the array and a second electrode (6;70) separated from the first electrode by a channel region underlying said floating gate, the first electrode, the second electrode and the channel region being formed in a layer of semiconductor material (5) of a first conductivity type and having a second conductivity type, comprising at least one ROM memory cell (2;200) which is identical to the electrically programmable non-volatile memory cells and is associated with a respective row and a respective column of the array, the ROM cell (2;200) comprising means for allowing or not allowing the electrical separation between said respective column and the second electrode (6';61) of the ROM cell (2;200), if the ROM cell must store a first logic state or, respectively, a second logic state.

    30.
    发明专利
    未知

    公开(公告)号：DE69913337T2

    公开(公告)日：2004-10-07

    申请号：DE69913337

    申请日：1999-07-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOMIERO ENRICO ,  PIO FEDERICO

    IPC: G11C16/12 ,  G11C16/10

    Abstract: The programming method comprises supplying a turnoff voltage to the source terminal of the selected cells when writing the cells. The turnoff voltage is a positive voltage of greater amplitude than the absolute value of the threshold voltage of the most written cell, i.e., the most depleted cell, taking into account the body effect. For example, the turnoff voltage may be 1 V greater than the absolute value of the threshold voltage of the most written cell. Advantageously, the turnoff voltage may be 5-6 V; to take into account the process, supply, and temperature variations, the turnoff voltage may be 7-8 V. The programming method is advantageously applicable to EEPROM memory devices with divided source lines, so as to apply the turnoff voltage only to the addressed byte or bytes, or to the page containing the addressed byte.

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