公开(公告)号：DE69739267D1

公开(公告)日：2009-04-02

申请号：DE69739267

申请日：1997-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： COLOMBO PAOLO ,  CAMERLENGHI EMILIO

IPC: H01L27/02 ,  H01L29/73 ,  H01L21/331 ,  H01L29/732 ,  H01L29/735

公开(公告)号：DE69534517D1

公开(公告)日：2006-02-23

申请号：DE69534517

申请日：1995-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BEZ ROBERTO ,  CAMERLENGHI EMILIO

IPC: H01L21/02 ,  H01L29/92 ,  H01L29/94

公开(公告)号：DE69426818D1

公开(公告)日：2001-04-12

申请号：DE69426818

申请日：1994-06-10

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CAMERLENGHI EMILIO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  H01L27/00 ,  G06F11/20

Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

公开(公告)号：ITMI20001567D0

公开(公告)日：2000-07-11

申请号：ITMI20001567

申请日：2000-07-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  BEZ ROBERTO ,  RATTI STEFANO

IPC: H01L21/8247 ,  H01L27/115

Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

公开(公告)号：ITMI982843A1

公开(公告)日：2000-06-29

申请号：ITMI982843

申请日：1998-12-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  COLABELLA ELIO

IPC: H01L21/8247 ,  H01L27/105

公开(公告)号：DE69325714T2

公开(公告)日：2000-03-02

申请号：DE69325714

申请日：1993-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  CASAGRANDE GIULIO

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.