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    22.
    发明专利
    未知

    公开(公告)号：DE602007005766D1

    公开(公告)日：2010-05-20

    申请号：DE602007005766

    申请日：2007-02-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  MARTIGNONE RICCARDO ,  NICOLLINI GERMANO

    IPC: H03H1/02 ,  H03H7/01

    Abstract: A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitance ((C var (REG_BUS)) and including a calibration loop (U_CV, CMP, TG_SAR), suitable to carry out a calibration cycle (C_LOOP) in several sequential steps (St_1, ..., St4), comprising: - a controllable capacitance unit (U_CV) suitable to receive a control signal (SAR_BUS) at the beginning of a calibration step and including an array of switched capacitors (C_AR1) that can be selectively activated by the control signal to be connected to a first common node (N_u) having, at the end of an integration interval (P2), a voltage value (VRC) depending on the total capacitance value of the activated capacitors; - an assessment unit (CMP) suitable to compare this voltage value (VRC) with a reference voltage to output a logic signal (OUT_CMP) that, based on the comparison result can be subjected to a transition between first and second logic levels; - a control and timing unit (TG_SAR) suitable to receive the logic signal (OUT_CMP) and to change the control signal (SAR_BUS) based thereon, in order to carry out a subsequent calibration step, characterized in that in said calibration step is provided, at the end of said integration interval (P2) a comparison interval (P3) of a preset duration, which allows a transition (tl,t4) of the logic signal (OUT_CMP) to occur prior to the beginning of said consecutive calibration step.

    23.
    发明专利
    未知

    公开(公告)号：DE602005014471D1

    公开(公告)日：2009-06-25

    申请号：DE602005014471

    申请日：2005-05-19

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO ,  MARTIGNONE RICCARDO

    IPC: H04M1/74 ,  H03M1/74 ,  H04B1/707

    Abstract: There is described a wide-band transmission system, particularly for employment in cellular telephony systems that adopt the WCDMA standard. The system comprises means for generating two digital signals containing information to be transmitted, means for converting into analog form the two signals comprising, for each signal to be converted, a digital-analog converter (DAC) followed by a low-pass filter (LOW-PASS), means for modulating both in phase and in quadrature a radio frequency carrier with the two signals issuing from the low-pass filters (LOW-PASS), and means for transmitting the modulated carrier in accordance with a predetermined emission mask. If the system is to be capable of being integrated into an area of small extent and is to have a low current consumption, the low-pass filter (LOW-PASS) is an active filter of the second order continuous in time and current-coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at a sampling frequency greater than the Nyquist frequency by at least as much as is necessary to respect the predetermined emission mask.

    26.
    发明专利
    未知

    公开(公告)号：AT303674T

    公开(公告)日：2005-09-15

    申请号：AT02743185

    申请日：2002-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  ZAMPROGNO MARCO ,  NAGARI ANGELO

    IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

    Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

    27.
    发明专利
    未知

    公开(公告)号：ITRM20010458A1

    公开(公告)日：2003-01-27

    申请号：ITRM20010458

    申请日：2001-07-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICCOLINI GERMANO ,  MARTIGNONE RICCARDO

    IPC: H03F1/30 ,  H03F3/45

    Abstract: The circuit comprises a differential amplifier with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal of the amplifier and the outputs there are connected first and second capacitors and first and second capacitive elements that by controlled switches are connected in parallel with, respectively, the first and second capacitors or alternately between first and second reference voltage terminals. The common mode output voltage is not exactly fixed at the beginning of the design, but is determined by attributing appropriate values to the first and second capacitive elements; more particularly, their capacitances C3 and C4 are chosen in such a way as to satisfy the following equality: Vcmn=Vrefl+[(Vrefp-Vrefm)/2]*(C 4 -C 3 )/(C 3 +C 4 ), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vrefl is the voltage of the second reference terminal.

    28.
    发明专利
    未知

    公开(公告)号：DE69430525T2

    公开(公告)日：2002-11-28

    申请号：DE69430525

    申请日：1994-05-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICOLLINI GERMANO

    IPC: G06F1/24 ,  G11C7/22 ,  H03K3/356 ,  H03K17/00 ,  H03K17/22 ,  G11C7/00

    Abstract: An initialization circuit for memory registers (2), being of the type which comprises a signal input (I) being applied a supply voltage (Vp) which rises linearly from a null value, and an initializing output (O) connected to an input of a memory register (2) and on which a voltage signal (Vd) being equal or proportional to the supply voltage (Vp), during the initialization step, and a null voltage signal, upon the supply voltage (Vp) dropping below a predetermined tripping value (Vs), are produced, further comprises, between the input (I) and the output (O): a first circuit portion (3) connected to the input (I), a second circuit portion (4) connected after the first and having a first output (D) connected to the initializing output (O), and a third, inverting circuit portion (7) having an input connected to a second output (C) of the second portion (4) and an output (E) connected to the first portion to even hold off that first portion (3) while the supply voltage drops below the threshold voltage (Vs).

    29.
    发明专利
    未知

    公开(公告)号：ITRM20010458D0

    公开(公告)日：2001-07-27

    申请号：ITRM20010458

    申请日：2001-07-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  NICCOLINI GERMANO ,  MARTIGNONE RICCARDO

    IPC: H03F1/30 ,  H03F3/45

    Abstract: The circuit comprises a differential amplifier with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal of the amplifier and the outputs there are connected first and second capacitors and first and second capacitive elements that by controlled switches are connected in parallel with, respectively, the first and second capacitors or alternately between first and second reference voltage terminals. The common mode output voltage is not exactly fixed at the beginning of the design, but is determined by attributing appropriate values to the first and second capacitive elements; more particularly, their capacitances C3 and C4 are chosen in such a way as to satisfy the following equality: Vcmn=Vrefl+[(Vrefp-Vrefm)/2]*(C 4 -C 3 )/(C 3 +C 4 ), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vrefl is the voltage of the second reference terminal.

    30.
    发明专利
    未知

    公开(公告)号：DE69424668D1

    公开(公告)日：2000-06-29

    申请号：DE69424668

    申请日：1994-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： NICOLLINI GERMANO ,  CONFALONIERI PIERANGELO

    IPC: H01L27/04 ,  H01L21/822 ,  H02M3/07 ,  H02M3/00

    Abstract: An output voltage stabilisation circuit for a voltage multiplier of the type comprising a first charge transfer capacitor (C1) designed to take and transfer electrical charges from the input terminal (IN) to the output terminal (OUT) of a second capacitor (C2) for charge storage connected between the output terminal (OUT) and ground comprises an integrator designed to generate a continuous voltage corresponding to the difference between a reference voltage (Vrif) and the output voltage (Vout) of the voltage multiplier and said continuous voltage is applied to one terminal of said charge transfer capacitor (C1).

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