公开(公告)号：DE69731089D1

公开(公告)日：2004-11-11

申请号：DE69731089

申请日：1997-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185 ,  H03F1/00

公开(公告)号：DE69731088D1

公开(公告)日：2004-11-11

申请号：DE69731088

申请日：1997-10-31

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  MARTIGNONI FABRIZIO ,  SCIAN ENRICO

IPC: H03K17/10 ,  H03K17/687 ,  H03K19/0175 ,  H03K19/0185 ,  H03F1/00

Abstract: The invention relates to a high-voltage final output stage (1) for driving an electric load, of the type which comprises a complementary pair (3) of transistors connected between first (Vdd) and second (Vss) supply voltage references, and at least one PMOS pull-up transistor (MP1) connected in series with an NMOS pull-down transistor (MN). The stage (1) comprises an additional PMOS transistor (MP2) connected in parallel with the pull-up transistor (MP1) and having the body terminal in common therewith. More particularly, the body terminals of both PMOS transistors (MP1,MP2) are formed in the semiconductor within a common well which can withstand high voltages, and the additional transistor (MP2) is a thick oxide PMOS power transistor.

公开(公告)号：DE69522926T2

公开(公告)日：2002-03-28

申请号：DE69522926

申请日：1995-05-02

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  CONTIERO CLAUDIO ,  ANDREINI ANTONIO

IPC: H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/00

Abstract: N-channel LDMOS and p-channel MOS devices for high voltage integrated in a BiCMOS integrated circuit and exploiting a RESURF condition are provided with a buried region of the same type of conductivity of the epitaxial layer and a doping level intermediate between the doping level of the epitaxial layer and of a source or drain region, respectively, of the high voltage complementary MOS devices. The devices may be configured as source or drain followers without problems.

公开(公告)号：IT1306973B1

公开(公告)日：2001-10-11

申请号：ITTO990009

申请日：1999-01-12

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  PALMIERI MICHELE

IPC: H01L21/762 ,  H01L21/8234

Abstract: A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and shaping the silicon oxide layer to form second delimiting walls inclined with respect to the substrate. The first walls have an angle of between approximately 70° and 110° with respect to the surface of the substrate; the second walls have an angle of between approximately 30° and 70° with respect to the surface of the substrate 11. The first delimiting walls are formed using a first mask and etching anisotropically first portions of the oxide layer; the second delimiting walls are formed using a second mask and carrying out a damage implantation for damaging second portions of the oxide layer and subsequently wet etching the damaged portions.

公开(公告)号：ITTO990009A1

公开(公告)日：2000-07-12

申请号：ITTO990009

申请日：1999-01-12

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  PALMIERI MICHELE

IPC: H01L21/762 ,  H01L21/8234

Abstract: A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and shaping the silicon oxide layer to form second delimiting walls inclined with respect to the substrate. The first walls have an angle of between approximately 70° and 110° with respect to the surface of the substrate; the second walls have an angle of between approximately 30° and 70° with respect to the surface of the substrate 11. The first delimiting walls are formed using a first mask and etching anisotropically first portions of the oxide layer; the second delimiting walls are formed using a second mask and carrying out a damage implantation for damaging second portions of the oxide layer and subsequently wet etching the damaged portions.

公开(公告)号：DE69415500T2

公开(公告)日：1999-05-20

申请号：DE69415500

申请日：1994-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMIERI MICHELE ,  DEPETRO RICCARDO

IPC: H01L21/8249 ,  H01L21/225 ,  H01L21/265 ,  H01L21/329 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/06 ,  H01L29/73 ,  H01L29/866 ,  H01L21/82

Abstract: A method is disclosed for forming a first region (32) with conductivity of a first type (N) and second, buried region (30) with conductivity of a second type (P) which forms a junction with the first region (32). By first and second doping steps, impurities of a first (As) and a second (B) type are successively introduced into a silicon chip. A high-temperature treatment causes the impurities thus introduced to diffuse and form said first (32) and second (30) regions. In order to provide a buried region whose concentration and/or depth are little dependent on process parameters, the second doping step comprises a first sub-step of low dosage and high energy implantation, and a second sub-step of low dosage and high energy implantation. The dosages and energies are such that they will not compensate or reverse the type of conductivity of the first region (32), and such that the concentration in the second region (30) will be substantially due to the second implantation step only. This process is compatible with a CMOS-process. The buried junction can be used for a Zener diode, a vertical bipolar transistor or a JFET.