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    21.
    发明专利
    未知

    公开(公告)号：ITTO991112A1

    公开(公告)日：2001-06-18

    申请号：ITTO991112

    申请日：1999-12-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

    IPC: H01L29/78

    Abstract: A transistor of the integrated MOS type with a high threshold voltage and low multiplication coefficient is formed in a chip that includes a substrate and defining an active area delimited by field oxide regions. The active area partially houses a tub having the same type of conductivity as the substrate and a greater doping level. In particular, the tub occupies a first half of the active area, while a second half of the active area is formed directly by the substrate. A gate region is present above the substrate and is isolated from the substrate by means of a gate oxide layer. The gate region is arranged partially above the second half of the active area and partially above the tub. The transistor also comprises a source region, which is formed in the tub on a first side of the gate region, and a drain region, which is arranged in the second half of the active area, on a second side of the gate region. Therefore, the transistor has a channel region which is delimited between the source region and drain region and one half of which has a first doping level and the other half a second doping level greater than the first doping level; consequently, the transistor has a high threshold voltage.

    22.
    发明专利
    未知

    公开(公告)号：DE69841040D1

    公开(公告)日：2009-09-17

    申请号：DE69841040

    申请日：1998-12-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  VAJANA BRUNO ,  DALLA LIBERA GIOVANNA ,  CREMONESI CARLO ,  GALBIATI NADIA

    IPC: H01L21/8239 ,  H01L21/8247 ,  H01L27/105

    Abstract: The step of forming source and drain regions (48', 55') for LV transistors includes the steps of forming sacrificial spacers (101) laterally to LV gate regions (43a); forming LV source and drain regions (55') in a self-aligned manner with the sacrificial spacers (101); removing the sacrificial spacers (101); forming HV gate regions (43d) of HV transistors; forming gate regions (43c) of selection transistors; forming control gate regions (43b) of memory transistors; simultaneously forming LDD regions (48') self-aligned with the LV gate regions (43a), HV source and drain regions (64) self-aligned with the HV gate regions (43d), source and drain regions (65a, 65b) self-aligned with the selection gate region (43c) and floating gate region (27b); depositing a dielectric layer; covering the HV and memory areas with a protection silicide mask (72); anisotropically etching the dielectric layer, to form permanent spacers (52') laterally to the LV gate regions (43a); removing the protection silicide mask (72); and forming silicide regions (75a1, 75a2) on the LV source and drain regions (48', 55') and on the LV gate regions (43a).

    24.
    发明专利
    未知

    公开(公告)号：DE69832162D1

    公开(公告)日：2005-12-08

    申请号：DE69832162

    申请日：1998-07-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  GALBIATI NADIA ,  DALLA LIBERA GIOVANNA ,  VAJANA BRUNO

    IPC: H01L27/06 ,  H01L21/8234

    Abstract: The manufacture process comprises the following steps in succession: depositing a gate oxide layer on a silicon substrate (2) defining a transistor area (5) and a resistor area (6); depositing a multicrystal silicon layer (11) on the gate oxide layer (10); removing selective portions of the multicrystal silicon layer (11) to form a gate region (11a) over the transistor area (5) and a protective region (11b) completely covering the resistor area (6); forming source and drain regions (22) in the transistor area (5), laterally to the gate region (11a); forming silicide regions (25, 26 and 27) on and in direct contact with the source and drain regions (22), the gate region (11a) and the protective region (11b); removing selective portions of the protective region (11b) to form a delimitation ring (34); and implanting ionic dopants in the resistor area (6), inside the area defined by the protective ring (34), to form a lightly doped resistor (38) which has no silicide regions directly on it.

    27.
    发明专利
    未知

    公开(公告)号：IT1302589B1

    公开(公告)日：2000-09-29

    申请号：ITMI982124

    申请日：1998-10-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PATELMO MATTEO ,  DALLA LIBERA GIOVANNA ,  GALBIATI NADIA ,  VAJANA BRUNO

    IPC: H01L21/8238

    Abstract: In a CMOS process for making dual gate transistors with silicide, high-voltage transistors with drain extensions are produced by first defining on a semiconductor substrate, active areas for low-voltage and high-voltage transistors. A gate oxide layer and a layer of polysilicon is deposited over the substrate, which is masked and etched to produce gates for the transistors. A dielectric layer is deposited to produce spacers to the sides of the transistor gate regions, then a mask partially shields the dielectric layer over the junctions of the high-voltage transistors while the spacers are being formed. Finally, the substrate is doped in the gate and active areas of the high-voltage transistor, and in the gate and active areas of the low-voltage transistor, except those areas that are blocked by the spacers.

    30.
    发明专利
    未知

    公开(公告)号：ITMI982082A1

    公开(公告)日：2000-03-29

    申请号：ITMI982082

    申请日：1998-09-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VAJANA BRUNO ,  CREMONESI CARLO ,  BOTTINI ROBERTA ,  DALLA LIBERA GIOVANNA

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on said integrated structure, an eighth stage of selective etching and removal of said second polysilicon layer in a region for said memory cell, and of said first and second polysilicon layers in said region for said circuitry transistor in order to form said circuitry transistor, and a ninth stage of selective etching and removal of said intermediate dielectric layer and of said first polysilicon layer in said region for said memory cell, wherein during said fifth stage said intermediate dielectric layer is etched and removed also in a region that is destined to form a channel of said selection transistor, and said sixth stage of ionic implantation therefore allows to introduce said dopant into said channel region and therefore to increase the threshold voltage of said selection transistor.

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