公开(公告)号：IT1401755B1

公开(公告)日：2013-08-02

申请号：ITTO20100723

申请日：2010-08-30

Applicant: ST MICROELECTRONICS SRL

Inventor： SAGGIO MARIO GIUSEPPE ,  FRISINA FERRUCCIO ,  MAGRI ANGELO

IPC: H01L29/78

公开(公告)号：ITTO20100724A1

公开(公告)日：2012-03-01

申请号：ITTO20100724

申请日：2010-08-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  MAGRI ANGELO ,  SAGGIO MARIO GIUSEPPE

公开(公告)号：ITTO20060329A1

公开(公告)日：2007-11-06

申请号：ITTO20060329

申请日：2006-05-05

Applicant: ST MICROELECTRONICS SRL

Inventor： MAGRI ANGELO ,  MARINO ANTONIO DAMASO MARIA

公开(公告)号：ITMI20042244A1

公开(公告)日：2005-02-19

申请号：ITMI20042244

申请日：2004-11-19

Applicant: ST MICROELECTRONICS SRL

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO ,  MAGRI ANGELO

公开(公告)号：DE69631524T2

公开(公告)日：2004-10-07

申请号：DE69631524

申请日：1996-07-05

Applicant: ST MICROELECTRONICS SRL

Inventor： MAGRI ANGELO ,  ZAMBRANO RAFFAELE ,  FRISINA FERRUCCIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/739

Abstract: A MOS technology power device comprises a semiconductor substrate (1), a semiconductor layer (2) of a first conductivity type superimposed over the semiconductor substrate (1), an insulated gate layer (5,6,7;51,52,6,7) covering the semiconductor layer (2), a plurality of substantially rectilinear elongated openings (10) parallel to each other in the insulated gate layer, a respective plurality of elongated body stripes (3) of a second conductivity type formed in the semiconductor layer (2) under the elongated openings (10), source regions (4) of the first conductivity type included in the body stripes (3) and a metal layer (9) covering the insulated gate layer and contacting the body stripes and the source regions through the elongated openings. Each body stripe comprises first portions (31) substantially aligned with a first edge of the respective elongated opening and extending under a second edge of the elongated opening to form a channel region, each first portion (31) including a source region (4) extending substantially from a longitudinal axis of symmetry of the respective elongated opening to the second edge of the elongated opening, and second portions (32), longitudinally intercalated with the first portions (31), substantially aligned with the second edge of the elongated opening and extending under the first edge of the elongated opening to form a channel region, each second portion including a source region extending substantially from the longitudinal axis of symmetry to the first edge of the elongated opening, the first portions (31) and second portions (32) of the body stripes (3) being respectively aligned in a direction transversal to the longitudinal axis.

公开(公告)号：ITMI20012284A1

公开(公告)日：2003-04-30

申请号：ITMI20012284

申请日：2001-10-30

Applicant: ST MICROELECTRONICS SRL

Inventor： FRISINA FERRUCCIO ,  PINTO ANTONIO ,  MAGRI ANGELO

IPC: H01L25/07 ,  H01L23/48 ,  H01L23/485 ,  H01L23/495 ,  H01L25/18 ,  H01L29/417

Abstract: The invention relates to an electronic power device (1) of improved structure and fabricated with MOS technology to have at least one gate finger region (3) and corresponding source regions (4) on opposite sides of the gate region (3). This device (1) has at least one first-level metal layer (3',4') arranged to independently contact the gate region (3) and source regions, and has a protective passivation layer (5) arranged to cover the gate region (3). Advantageously, a wettable metal layer (7), deposited onto the passivation layer (5) and the first-level metal layer (4'), overlies said source regions (4). In this way, the additional wettable metal layer (7) is made to act as a second-level metal.