公开(公告)号：EP1058303A1

公开(公告)日：2000-12-06

申请号：EP99830334.1

申请日：1999-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/266

CPC classification number: H01L29/7802 ,  H01L21/266 ,  H01L29/1095 ,  H01L29/66712

Abstract: A process for fabricating a VDMOS structure comprising the steps of forming a body region of a first conductivity type (p-) by implanting and diffusing a dopant (B) through a first aperture defined by the edges of a patterned gate conductor layer (4) on a dielectric gate layer (3) formed on the surface of an epitaxial layer (n). forming region (p+) with a higher dopant concentration within said body region (p-) by implanting dopant at a high kinetic energy down to a certain depth from the surface of the epitaxial layer, implanting and diffusing source regions of a second conductivity type (n+) in said body region (p-) projectively above said region of higher doping level (p+), comprises the following steps:

forming a resist mask (Ms) defining apertures for implanting said source regions prior to the formation of said region (p+) of higher doping level:
implanting through said resist mask (Ms), said dopant of a second conductivity type (n+) in a superficial zone of said body region (p-). and a dopant of said first conductivity type at a kinetic energy sufficient to implant the dopant (p+) at a depth below said superficial zone implanted with a dopant (n-) of the second conductivity type;
annealing at a temperature and for a time sufficient to form (n+) source/ (p-) body junctions above body regions (p+) of a relatively high dopant concentration (p+).

An effective reduction of the gain of the parasite transistor is achieved without the need of a dedicated masking step.

Abstract translation: 一种用于制造VDMOS结构的方法，包括以下步骤：通过将掺杂剂（B）通过由图案化的栅极导体层（4）的边缘限定的第一孔注入和扩散而形成第一导电类型（p-）的体区， 在形成在外延层（n）的表面上的电介质栅极层（3）上。 通过以高动能将掺杂剂注入到距离外延层的表面一定深度的方式，在所述体区（p-）中具有较高掺杂剂浓度的形成区（p +），注入和扩散第二导电类型的源区（ n +）在所述体积区域（p-）中高于所述掺杂浓度较高的区域（p +），包括以下步骤：形成在形成所述区域（p +）之前形成用于注入所述源极区域的孔的抗蚀剂掩模（Ms） ）：通过所述抗蚀剂掩模（Ms），在所述体区（p-）的表面区域中注入第二导电类型（n +）的所述掺杂剂。 和所述第一导电类型的掺杂剂，其动能足以在注入第二导电类型的掺杂剂（n-）的所述浅表区下方的深度处注入掺杂剂（p +）; 在足以在较高掺杂剂浓度（p +）的体区（p +）之上形成（n +）源/（p-）体结的温度和时间退火。 实现了寄生晶体管的增益的有效减少，而不需要专门的掩蔽步骤。

公开(公告)号：EP1011146A1

公开(公告)日：2000-06-21

申请号：EP98830739.3

申请日：1998-12-09

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio

IPC: H01L29/06 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/66712 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, comprising a first step of forming a first semiconductor layer (41) of a first conductivity type, a second step of forming a first mask (37) over the top surface of the first semiconductor layer (41), a third step of removing portions of the first mask (37) in order to form at least one opening (51) in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer (41) through the at least one opening (51), a fifth step of completely removing the first mask (37) and of forming a second semiconductor layer (42) of the first conductivity type over the first semiconductor layer (41), a sixth step of diffusing the dopant implanted in the first semiconductor layer (41) in order to form a doped region (220) of the second conductivity type in the first and second semiconductor layers (41, 42). The second step up to the sixth step are repeated at least one time in order to form a final edge structure comprising a number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) of the first conductivity type and at least two columns of doped regions (220, 230, 240, 250, 260) of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) and formed by means of superimposition of the doped regions (220, 230, 240, 250, 260) subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther to the high voltage semiconductor device.

Abstract translation: 制造高电压半导体器件的边缘结构的方法，包括形成第一导电类型的第一半导体层（41）的第一步骤，在第一导电类型的顶表面上形成第一掩模（37）的第二步骤 半导体层（41），第三步骤，去除第一掩模（37）的部分以形成其中的至少一个开口（51）;第四步骤，在第一半导体层中引入第二导电类型的掺杂剂 41）通过所述至少一个开口（51），第五步骤，在所述第一半导体层（41）上完全去除所述第一掩模（37）并形成所述第一导电类型的第二半导体层（42），第六步骤 扩散注入第一半导体层（41）中的掺杂剂的步骤，以在第一和第二半导体层（41,42）中形成第二导电类型的掺杂区域（220）。 至少一次重复第六步骤的第二步骤，以便形成包括第一导电类型的多个重叠半导体层（41,42,43,44,45,46）的最终边缘结构，并且至少 两列第二导电类型的掺杂区域（220,230,240,250,260），所述列以多个叠加的半导体层（41,42,43,44,45,46）插入并且通过装置形成 随后通过掩模开口注入的掺杂区域（220,230,240,250,260）的叠加，高压半导体器件附近的色谱柱比高于高压半导体器件的色谱柱深。

公开(公告)号：EP2604729A1

公开(公告)日：2013-06-19

申请号：EP12195884.7

申请日：2012-12-06

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Abbondanza, Giuseppe

IPC: C30B33/00 ,  C30B33/06

CPC classification number: H01L21/7806 ,  C23C16/01 ,  C23C16/0218 ,  C23C16/325 ,  C23C16/4583 ,  C30B9/06 ,  C30B19/04 ,  C30B19/08 ,  C30B19/12 ,  C30B29/36 ,  C30B33/00 ,  C30B33/06 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02609

Abstract: Method for producing a wafer of a first semiconductor material (515). Said first semiconductor material has a first melting temperature. The method comprises providing a crystalline substrate (102) of a second semiconductor material having a second melting temperature lower than the first melting temperature, and exposing the crystalline substrate to a flow of first material precursors for forming a first layer (510) of the first material on the substrate. The method further comprising bringing the crystalline substrate to a first process temperature higher than the second melting temperature, and at the same time lower than the first melting temperature, in such a way the second material melts, separating the second melted material from the first layer, and exposing the first layer to the flow of the first material precursor for forming a second layer (530) of the first material on the first layer.

Abstract translation: 第一半导体材料（515）的晶片的制造方法。 所述第一半导体材料具有第一熔融温度。 该方法包括提供具有低于第一熔融温度的第二熔化温度的第二半导体材料的结晶衬底（102），并将该晶体衬底暴露于第一材料前体流中，以形成第一熔化温度的第一层（510） 材料在基板上。 该方法还包括使晶体衬底处于高于第二熔化温度的第一工艺温度，并且同时低于第一熔化温度，以这种方式，第二材料熔化，将第二熔化材料与第一层分离 并且将第一层暴露于第一材料前体的流动，以形成第一层上的第一材料的第二层（530）。

公开(公告)号：EP1742258A1

公开(公告)日：2007-01-10

申请号：EP05425493.3

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Saggio, Mario Giuseppe ,  Frisina, Ferruccio ,  Rascuna, Simone

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66712

Abstract: Process for manufacturing a multi-drain power electronic device (30) integrated on a semiconductor substrate (100) of a first type of conductivity, comprising the following steps:
forming a first semiconductor layer (21) of the first type of conductivity and of a first resistivity (ρ 1 ) value on the semiconductor substrate (100),
forming at least a second semiconductor layer (22) of a second type of conductivity of a second resistivity (ρ 2 ) value on the first semiconductor layer (21),
forming, in this at least a second semiconductor layer (22), a first plurality of implanted regions (D1) of the first type of conductivity by means of a first selective implant step with a first implant dose (Φ 1 ) ,
forming, above this at least a second semiconductor layer (22), a superficial semiconductor layer (26) of the first type of conductivity of a third resistivity (ρ 6 ) value,
forming in the surface semiconductor layer (26) body regions (40) of the second type of conductivity, the body regions (40) being aligned with portions of the semiconductor layer (22) free from the plurality of implanted regions (D1),
carrying out a thermal diffusion step so that the plurality of implanted regions (D1) form a plurality of electrically continuous implanted column regions (D) along this at least a second semiconductor layer (22), the plurality of column implanted regions (D) delimiting a plurality of column regions (50) of the second type of conductivity aligned with the body regions (40).

Abstract translation: 用于制造集成在第一导电类型的半导体衬底（100）上的多漏功率电子器件（30）的工艺，包括以下步骤：形成第一导电类型的第一半导体层（21）和第一导电类型的第一半导体层 在所述半导体衬底（100）上的第一电阻率（ρ1）值，在所述第一半导体层（21）上形成至少第二电阻率（ρ2）值的第二导电类型的第二半导体层（22），从而形成 通过具有第一注入剂量（Φ1）的第一选择注入步骤在该至少第二半导体层（22）上形成具有第一导电类型的第一多个注入区域（D1），在该至少一个注入区域 第二半导体层（22）;第三电阻率（ρ6）值的第一导电类型的表面半导体层（26），其在表面半导体层（26）中形成第二导电类型的体区域（40） 身体部位（ 40）与没有所述多个注入区域（D1）的所述半导体层（22）的部分对准，执行热扩散步骤，使得所述多个注入区域（D1）形成多个电连续注入柱区域 D）沿所述至少第二半导体层（22）延伸，所述多个列注入区（D）限定与所述体区（40）对齐的所述第二导电类型的多个列区（50）。

公开(公告)号：EP1742249A1

公开(公告)日：2007-01-10

申请号：EP05425495.8

申请日：2005-07-08

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Saggio, Mario Giuseppe

IPC: H01L21/04 ,  H01L29/78 ,  H01L29/24 ,  H01L29/423

CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068

Abstract: Method for manufacturing a vertical power MOS transistor on a semiconductor substrate (10) with wide band gap comprising a first superficial semiconductor layer (11) with wide band gap of a first type of conductivity, comprising the steps of:
- forming trench regions (13) in the first superficial semiconductor layer (11),
- filling in said trench regions (13) by means of a second semiconductor layer (14) with wide band gap of a second type of conductivity, so as to form semiconductor portions (15) of the second type of conductivity contained in the first superficial semiconductor layer (11),
- carrying out at least one ion implantation of a first type of dopant in the semiconductor portions (15) for forming respective implanted body regions (19) of said second type of conductivity,
- carrying out at least one ion implantation of a second type of dopant in each of the implanted body regions (19) for forming at least one implanted source region (23) of the first type of conductivity inside the implanted body regions (19),
- carrying out an activation thermal process of the first and second type of dopant with low thermal budget suitable to complete said formation of the implanted body and source regions (19,23).

Abstract translation: 1。一种用于在具有宽带隙的半导体衬底（10）上制造垂直功率MOS晶体管的方法，所述宽带隙包括具有第一导电类型的宽带隙的第一表面半导体层（11），所述方法包括以下步骤： - 形成沟槽区域 ）在第一表面半导体层（11）中， - 通过具有第二导电类型的宽带隙的第二半导体层（14）填充所述沟槽区域（13），从而形成半导体部分（15） 包含在所述第一表面半导体层（11）中的第二导电类型， - 在所述半导体部分（15）中执行至少一次第一类型掺杂物的离子注入，以形成所述第二表面 - 在每个注入体区（19）中进行至少一次第二类型掺杂剂的离子注入，以形成至少一个第一类型导电性绝缘体的注入源区（23） （19）， - 以低热预算执行第一和第二类型掺杂物的激活热处理，适于完成所述注入体区和源区（19,23）的所述形成。

公开(公告)号：EP1659638A1

公开(公告)日：2006-05-24

申请号：EP05025288.1

申请日：2005-11-18

Applicant: STMicroelectronics S.r.l.

Inventor： Magri', Angelo ,  Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L21/2815 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66712

Abstract: Power MOS device of the type comprising a plurality of elementary power MOS transistors (2) having respective gate structures (12) and comprising a gate oxide (7) with double thickness having a thick central part (8) and lateral portions (9) of reduced thickness. Such device exhibiting gate structures (12) comprising first gate conductive portions (13) overlapped onto said lateral portions (9) of reduced thickness to define, for the elementary Mos transistors (2), the gate electrodes, as well as a conductive structure or mesh (14). Such conductive structure (14) comprising a plurality of second conductive portions (15) overlapped onto the thick central part (8) of gate oxide (7) and interconnected to each other and to the first gate conductive portions (13) by means of a plurality of conducive bridges (16). The present invention further relates to a method for realising the power MOS device.

Abstract translation: 该功率MOS器件包括具有各自的栅极结构（12）的多个基本功率MOS晶体管（2），并且包括具有厚度为中心部分（8）的厚度的双层厚度的栅极氧化物（7）和侧壁部分 减小厚度。 这种具有栅极结构（12）的器件包括第一栅极导电部分（13），该第一栅极导电部分重叠在所述侧面部分（9）上以减小厚度，以限定基本的MOS晶体管（2），栅极电极以及导电结构 网格（14）。 这种导电结构（14）包括多个第二导电部分（15），其重叠在栅极氧化物（7）的厚的中心部分（8）上并且通过一个第二栅极导电部分（13）彼此互连并连接到第一栅极导电部分 多个有利桥梁（16）。 本发明还涉及实现功率MOS器件的方法。

公开(公告)号：EP1011146B1

公开(公告)日：2006-03-08

申请号：EP98830739.3

申请日：1998-12-09

Applicant: STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio

IPC: H01L29/06 ,  H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/66712 ,  H01L29/7802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, comprising a first step of forming a first semiconductor layer (41) of a first conductivity type, a second step of forming a first mask (37) over the top surface of the first semiconductor layer (41), a third step of removing portions of the first mask (37) in order to form at least one opening (51) in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer (41) through the at least one opening (51), a fifth step of completely removing the first mask (37) and of forming a second semiconductor layer (42) of the first conductivity type over the first semiconductor layer (41), a sixth step of diffusing the dopant implanted in the first semiconductor layer (41) in order to form a doped region (220) of the second conductivity type in the first and second semiconductor layers (41, 42). The second step up to the sixth step are repeated at least one time in order to form a final edge structure comprising a number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) of the first conductivity type and at least two columns of doped regions (220, 230, 240, 250, 260) of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers (41, 42, 43, 44, 45, 46) and formed by means of superimposition of the doped regions (220, 230, 240, 250, 260) subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther to the high voltage semiconductor device.

公开(公告)号：EP1258927A1

公开(公告)日：2002-11-20

申请号：EP01830308.1

申请日：2001-05-15

Applicant: STMicroelectronics S.r.l.

Inventor： Coffa, Salvatore ,  Libertino, Sebania ,  Frisina, Ferruccio

IPC: H01L31/107 ,  H01L31/0288

CPC classification number: H01L31/107 ,  H01L31/0288 ,  Y02B10/10 ,  Y02E10/50

Abstract: The high-gain photodetector (1) is formed in a semiconductor-material body (5) which houses a PN junction (13, 14) and a sensitive region (19) that is doped with rare earths, for example erbium (Er). The PN junction (13, 14) forms an acceleration and gain region (13, 14) separate from the sensitive region (19). The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region (19). Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction (13-14), which is transparent to light, can be captured by an erbium ion in the sensitive region (19), so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.

Abstract translation: 高增益光电检测器（1）形成在容纳PN结（13,14）的半导体材料体（5）中，以及掺杂有稀土（例如铒）的敏感区域（19）。 PN结（13,14）形成与敏感区域（19）分离的加速度和增益区域（13,14）。 PN结被反向偏置并且产生容纳敏感区域（19）的大量耗尽区域。 因此，具有等于所使用的稀土的吸收频率的频率的入射光子穿过透明的PN结（13-14）可以被敏感区域（19）中的铒离子捕获，因此 以产生通过存在的电场朝向PN结加速的初级电子，并且可以根据雪崩过程通过冲击产生二次电子。 因此，单个光子可以产生级联的电子，从而显着提高检测效率。

公开(公告)号：EP0782201B1

公开(公告)日：2000-08-30

申请号：EP95830542.7

申请日：1995-12-28

Applicant: STMicroelectronics S.r.l. ,  Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno

Inventor： Grimaldi, Antonio ,  Schillaci, Antonino ,  Frisina, Ferruccio ,  Ferla, Giuseppe

IPC: H01L29/78 ,  H01L29/739 ,  H01L29/423 ,  H01L29/417 ,  H01L23/482 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L23/4824 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41725 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A MOS-technology power device integrated structure comprises a plurality of elementary functional units formed in a semiconductor material layer (3) of a first conductivity type. The elementary functional units comprise body stripes (9;90) of a second conductivity type extending substantially parallely to each other and source regions (14;140) of the first conductivity type. A conductive gate layer (17;170) is insulatively disposed over the semiconductor material layer (3) between the body stripes (9;90). A mesh (4;40) of the second conductivity type is formed in the semiconductor material layer (3) and comprises an annular frame region (5;50) surrounding the plurality of body stripes (9;90) and at least one first elongated stripe (7;60) extending within the annular frame region (5;50) in a direction substantially orthogonal to the body stripes (9;90) and merged with the annular frame region (5;50), the body stripes (9;90) being divided by the first elongated stripe (7;60) in two respective groups and being merged with the mesh (4;40). A conductive gate finger (25;250) connected to said conductive gate layer (17;170) insulatively extends over the first elongated stripe (7;60). Source metal plates (20;200) are provided covering each group of parallel body stripes and contacting each body stripe of the group. The conductive gate finger (25;250) is covered and contacted by a respective metal gate finger (27;270).

公开(公告)号：EP0772244B1

公开(公告)日：2000-03-22

申请号：EP95830468.5

申请日：1995-11-06

Applicant: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno ,  STMicroelectronics S.r.l.

Inventor： Frisina, Ferruccio ,  Ferla, Giuseppe ,  Rinaudo, Salvatore

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/66712

Abstract: A MOS technology power device comprises a plurality of elementary functional units, each elementary functional unit comprising a body region (3) of a first conductivity type formed in a semiconductor material layer (2) of a second conductivity type having a first resistivity value. Under each body region (3) a respective lightly doped region (20) of the second conductivity type is provided having a second resistivity value higher than said first resistivity value.