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    Self-aligned process for manufacturing a phase change memory cell and phase change memory cell thereby manufactured
    23.
    发明公开
    Self-aligned process for manufacturing a phase change memory cell and phase change memory cell thereby manufactured 有权
    制造相变存储单元的自对准方法，和由此制得相变存储单元

    公开(公告)号：EP1469532A1

    公开(公告)日：2004-10-20

    申请号：EP03425235.3

    申请日：2003-04-16

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio

    IPC: H01L45/00 ,  H01L27/24 ,  G11C11/34 ,  H01L27/10

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/101 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683 ,  H01L45/1691

    Abstract: A process for manufacturing a phase change memory cell, comprising the steps of: forming a resistive element (22); forming a delimiting structure (48, 49, 55a) having an aperture (56) over the resistive element (22); forming a memory portion (38a) of a phase change material in the aperture, the resistive element (22) and the memory portion (38a) being in direct electrical contact and defining a contact area (58) of sublithographic extension. The step of forming a memory portion (38a) further includes filling the aperture (56) with the phase change material and removing from the delimiting structure (48, 49, 55a) an exceeding portion (38b) of the phase change material exceeding the aperture (56).

    Abstract translation: 一种用于制造相变存储单元的方法，包括以下步骤：形成一电阻元件（22）; 上形成具有开口（56）在所述电阻元件（22）上的限制结构（48,49，55A）; 形成相变材料的孔中的存储器部分（38A），电阻元件（22）和存储部分（38A）直接电接触和限定亚光刻延伸的接触区域（58）。 形成存储器部分（38A）还包括填充与相变材料中的孔（56）和从所述限制结构（48,49，55A）上超过部分中的相变材料的（38B）超过孔径去除步骤 （56）。

    Contact structure, phase change memory cell, and manufacturing method thereof with elimination of double contacts
    24.
    发明公开
    Contact structure, phase change memory cell, and manufacturing method thereof with elimination of double contacts 有权
    接触结构，相变存储器单元，并用消除双触点及其制造方法

    公开(公告)号：EP1339111A9

    公开(公告)日：2004-01-28

    申请号：EP02425089.6

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: G11C11/5678 ,  G11C11/56 ,  G11C13/0004 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: The phase change memory cell (5) is formed by a resistive element (22) and by a memory region (38) of a phase change material. The resistive element has a first thin portion having a first sublithographic dimension in a first direction (Y); and the memory region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) which is transverse to said first direction. The first and second thin portions (22, 38a) are in direct electrical contact and define a contact area (58) having sublithographic extent. The second thin portion (38a) is formed in a slit of sublithograhic dimensions. According to a first solution, oxide spacer portions (55a) are formed in a lithographic opening (51), delimited by a mold layer (49). According to a different solution, a sacrificial region is formed on top of a mold layer and is used for forming the sublithographic slit in the mold layer.

    Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof
    25.
    发明公开
    Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof 有权
    亚光刻接触结构，具有优化的加热结构相变存储单元，以及它们的制备方法

    公开(公告)号：EP1339103A1

    公开(公告)日：2003-08-27

    申请号：EP02425088.8

    申请日：2002-02-20

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Casagrande, Giulio ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: H01L23/522 ,  H01L23/528 ,  H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    Abstract: An electronic semiconductor device has a sublithographic contact area (45, 58) between a first conductive region (22) and a second conductive region (38). The first conductive region (22) is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area (45, 58). The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

    Abstract translation: 一种电子半导体器件具有第一导电区（22）和一个第二导电区（38）之间的亚光刻的接触面积（45，58）。 第一导电区（22）是杯形，并具有垂直壁延伸，在俯视图中，沿着细长形状的封闭线。 一个第一导电区域的壁的形成第一薄壁部，并且具有在第一方向上的第一尺寸。 第二导电区域（38）具有在第二方向上的第二亚光刻尺寸（X）横向于第一尺寸的第二薄壁部（38A）。 所述第一和第二导电区域在其薄的部分直接电接触，并形成亚光刻接触区域（45，58）。 细长形状在第一方向上的矩形和椭圆形的细长之间选择。 因此，接触区域的尺寸，即使在掩模之间的小的未对准的存在保持大致恒定，限定导电区域。

    Phase change memory device for multibit storage
    29.
    发明公开
    Phase change memory device for multibit storage 有权
    Phasenwechsel-SpeichervorrichtungfürMultibit-Speicherung

    公开(公告)号：EP2034536A1

    公开(公告)日：2009-03-11

    申请号：EP07425555.5

    申请日：2007-09-07

    Applicant: STMicroelectronics S.r.l. ,  Politecnico di Milano

    Inventor： Redaelli, Andrea ,  Pellizzer, Fabio ,  Pirovano, Agostino

    IPC: H01L45/00

    CPC classification number: H01L45/1233 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144

    Abstract: A phase change memory device (10) having a heater element (2) and memory region (3) of chalcogenic material. The memory region has a phase changing portion (5) in electrical and thermal contact with the heater element and forms a first current path between the heater element and a rest portion (4) of the memory element. The phase changing portion (5) has a dimension correlated to information stored in the memory region and a higher resistivity than the rest portion (4). A parallel current path (11) extends between the heater element (2) and the rest portion (4) of said memory element and has a resistance depending upon the dimension of the phase changing portion (5) and lower than the phase changing portion (5), thus modulating the overall resistance of phase change memory device.

    Abstract translation: 具有加热器元件（2）和存储区域（3）的相变材料的相变存储器件（10）。 存储区域具有与加热器元件电接触和热接触的相变部分（5），并且在加热器元件和存储元件的其余部分（4）之间形成第一电流路径。 相位改变部分（5）具有与存储在存储区域中的信息相关的维度，并且比其余部分（4）具有更高的电阻率。 平行电流路径（11）在加热器元件（2）和所述存储元件的其余部分（4）之间延伸，并且具有取决于相变部分（5）的尺寸并且低于相变部分 5），从而调制相变存储器件的整体电阻。

    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions
    30.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions 审中-公开
    对于具有选择晶体管的双极单元阵列具有突出的导电区域的制造方法

    公开(公告)号：EP2015357A1

    公开(公告)日：2009-01-14

    申请号：EP07425423.6

    申请日：2007-07-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Benvenuti, Augusto ,  Cappelletti, Paolo ,  Bez, Roberto ,  Pirovano, Agostino

    IPC: H01L21/8229 ,  H01L27/102 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

    Abstract: A process for manufacturing an array of cells in a body (1) of semiconductor material wherein a common conduction region (11) of a first conductivity type and a plurality of shared control regions (12), of a second conductivity type, are formed in the body. The shared control regions (12) extend on the common conduction region (11) and are laterally delimited by insulating regions (32). Then, a grid-like layer (36) is formed on the body (1) to delimit a first plurality of empty regions (38) directly overlying the body and conductive regions of semiconductor material and the first conductivity type (44) are formed by filling the first plurality of empty regions (38), each conductive region forming, together with the common conduction region and an own shared control region (12), a bipolar junction transistor (20).

    Abstract translation: 于一体的制造单元的阵列的方法（1）的半导体材料的worin的第一导电类型的公共导电区（11）和一个第二导电类型的共享控制区域（12）的复数，在形成 身体。 共享控制区（12）上的公共导电区（11）延伸，并且尾盘反弹通过绝缘区域（32）分隔。 然后，网格状层（36）形成在所述主体（1）来分隔空区域的第一多个（38）直接覆盖所述主体和半导体材料的导电区域和第一导电类型（44）由形成 填充空区域（38），每个导电区域上形成的第一多个，与普通传导区在一起并且连接到自己的共享控制区域（12），双极结型晶体管（20）。

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