中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.019 seconds)

    Process for manufacturing an array of cells including selection bipolar junction transistors
    1.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors 有权
    用于与所述选择晶体管的双极电池装置和相关联的小区布置的制造方法

    公开(公告)号：EP1408549A1

    公开(公告)日：2004-04-14

    申请号：EP02425604.2

    申请日：2002-10-08

    Applicant: STMicroelectronics S.r.l. ,  OVONYX Inc.

    Inventor： Pellizzer, Fabio ,  Casagrande, Guilio ,  Gastaldi, Roberto ,  Vendrame, Loris ,  Benvenuti, Augusto ,  Lowrey, Tyler, c/o Ovonyx Inc.

    IPC: H01L27/10 ,  H01L29/68 ,  H01L45/00

    CPC classification number: H01L29/685 ,  H01L27/101 ,  H01L27/24

    Abstract: A process for manufacturing an array of cells, including: implanting, in a body (10) of semiconductor material of a first conductivity type, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conduction region, a plurality of active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer (21) having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings (27a) with a doping agent of the first conductivity type, thereby forming, in the active area regions, second conduction regions (14) of the first conductivity type; implanting second portions of the active area regions through the second openings (27b) with a doping agent of the second conductivity type, thereby forming control contact regions (15) of the second conductivity type and a second doping level, higher than the first doping level; forming, on top of the body, a plurality of storage components (3), each storage component having a terminal connected to a respective second conduction region (14).

    Abstract translation: 单元的阵列是通过注入第一导电类型，以通过绝缘层的第一开口有源区区域的第一部分的掺杂剂，以形成第二导电区制成; 注入第二导电类型到穿过绝缘层以形成控制接触区域的第二开口的有源区域的区域的第二部分中的掺杂剂; 和在所述主体的顶部上形成存储元件。 单元阵列的制造包括：提供第一导电类型的半导体材料的本体（10）; 植入在身体中，第一导电类型的公共导电区（11）; 形成在所述主体中，公共导电区域上方，有源区的区域的第二导电类型和第一掺杂水平的（12）; 形成，在所述主体的顶部，绝缘层上具有第一和第二开口（27A，27B）; 通过用第一导电类型的掺杂剂的第一开口注入所述有源区区域的第一部分，从而形成在所述有源区区域中的第一导电类型的第二传导区域; 通过注入与所述第二导电类型的掺杂剂的第二孔中的活性区域的区域的第二部分，所述第二导电类型和第二掺杂水平比所述第一掺杂等级高的形成，从而控制接触区域（15）; 并形成存储元件（24）在所述主体的顶部上。 每个控制接触区域形成，与所述第二传导区域和公共传导区，选择双极型晶体管（20）连接在一起。 每个存储组件具有连接到第二respectivement传导区的端子。 它定义，与双极晶体管，所述单元阵列的细胞一起。

    A memory device with unipolar and bipolar selectors
    2.
    发明公开
    A memory device with unipolar and bipolar selectors 有权
    Speiherannnung mit unipolaren和bipolaren Auswahlschaltungen

    公开(公告)号：EP1640994A1

    公开(公告)日：2006-03-29

    申请号：EP04104595.6

    申请日：2004-09-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Benvenuti, Augusto ,  Vendrame, Loris ,  Zuliani, Paola

    IPC: G11C16/02 ,  G11C11/34

    CPC classification number: G11C13/0004 ,  G11C13/003 ,  G11C2213/76 ,  G11C2213/79

    Abstract: A memory device is proposed. The memory device includes a plurality of memory cells (P,S), wherein each memory cell includes a storage element (P) and a selector (S) for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element (M) and a bipolar element (D;B). The memory device further includes control means (110s) for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

    Abstract translation: 提出了一种存储器件。 存储器件包括多个存储器单元（P，S），其中每个存储器单元包括用于在读取操作或编程操作期间选择相应的存储元件的存储元件（P）和选择器（S）。 选择器包括单极元件（M）和双极元件（D; B）。 存储器件还包括控制装置（110s），用于在编程操作期间在读取操作期间使单极元件能够被普遍使能或双极元件。

    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions
    3.
    发明公开
    Process for manufacturing an array of cells including selection bipolar junction transistors with projecting conduction regions 审中-公开
    对于具有选择晶体管的双极单元阵列具有突出的导电区域的制造方法

    公开(公告)号：EP2015357A1

    公开(公告)日：2009-01-14

    申请号：EP07425423.6

    申请日：2007-07-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pellizzer, Fabio ,  Benvenuti, Augusto ,  Cappelletti, Paolo ,  Bez, Roberto ,  Pirovano, Agostino

    IPC: H01L21/8229 ,  H01L27/102 ,  H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/1022 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233

    Abstract: A process for manufacturing an array of cells in a body (1) of semiconductor material wherein a common conduction region (11) of a first conductivity type and a plurality of shared control regions (12), of a second conductivity type, are formed in the body. The shared control regions (12) extend on the common conduction region (11) and are laterally delimited by insulating regions (32). Then, a grid-like layer (36) is formed on the body (1) to delimit a first plurality of empty regions (38) directly overlying the body and conductive regions of semiconductor material and the first conductivity type (44) are formed by filling the first plurality of empty regions (38), each conductive region forming, together with the common conduction region and an own shared control region (12), a bipolar junction transistor (20).

    Abstract translation: 于一体的制造单元的阵列的方法（1）的半导体材料的worin的第一导电类型的公共导电区（11）和一个第二导电类型的共享控制区域（12）的复数，在形成 身体。 共享控制区（12）上的公共导电区（11）延伸，并且尾盘反弹通过绝缘区域（32）分隔。 然后，网格状层（36）形成在所述主体（1）来分隔空区域的第一多个（38）直接覆盖所述主体和半导体材料的导电区域和第一导电类型（44）由形成 填充空区域（38），每个导电区域上形成的第一多个，与普通传导区在一起并且连接到自己的共享控制区域（12），双极结型晶体管（20）。

    Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device
    4.
    发明公开
    Array of vertical bipolar junction transistors, in particular selectors in a phase change memory device 审中-公开
    矩阵vert er er ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung ung

    公开(公告)号：EP1965427A1

    公开(公告)日：2008-09-03

    申请号：EP07425107.5

    申请日：2007-02-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Magistretti, Michele ,  Pellizzer, Fabio ,  Benvenuti, Augusto

    IPC: H01L27/102

    CPC classification number: H01L27/1022 ,  H01L21/76205 ,  H01L21/76224 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

    Abstract: A process for manufacturing an array of bipolar transistors, wherein deep field insulation regions (26) of dielectric material are formed in a semiconductor body (21), thereby defining a plurality of active areas (22), insulated from each other and a plurality of bipolar transistors are formed in each active area. In particular, in each active area, a first conduction region (24) is formed at a distance from the surface of the semiconductor body (21); a control region (25) is formed on the first conduction region (24); and, in each control region, at least two second conduction regions (31) and at least one control contact region (36) are formed. The control contact region (36) is interposed between the second conduction regions (31) and at least two surface field insulation regions (29) are thermally grown in each active area (22) between the control contact region (36) and the second conduction regions (31).

    Abstract translation: 一种用于制造双极晶体管阵列的方法，其中介电材料的深场绝缘区域（26）形成在半导体本体（21）中，从而限定出彼此绝缘的多个有源区域（22）和多个 在每个有效区域中形成双极晶体管。 特别地，在每个有源区域中，形成与半导体本体（21）的表面相距一定距离的第一导电区域（24）。 在所述第一导电区域（24）上形成控制区域（25）。 并且在每个控制区域中形成至少两个第二导电区域（31）和至少一个控制接触区域（36）。 控制接触区域（36）介于第二导电区域（31）之间，并且至少两个表面场绝缘区域（29）在控制接触区域（36）和第二导电区域（36）之间的每个有源区域（22）中热生长 地区（31）。

Patent Agency Ranking