公开(公告)号：JPH09146905A

公开(公告)日：1997-06-06

申请号：JP14525096

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： UIRIAMU JIYOERU WATOSON ,  UIRIAMU EDOWAADO BEIKAA ,  UIRIAMU EFU BURUTSUKAATO ,  UIRIAMU PATAASON BANTON ,  DEIBUITSUDO JIEI GAASHIA ,  ROBAATO DABURIYUU HOOSUTO ,  JIEFURII AI ISUWANDEII ,  DEIBUITSUDO KINKEIDO

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/163 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To obtain a multiplex processor system combining the both of two approaches with a fault telerant architecture, a hardware redundancy and a software recovery technique by a single system. SOLUTION: A multiprocessor system 10 includes a number of sub-processor systems 10A and 10B each of which is substantially composed into the same one. The one CPU 12 is the sub-processor systems 10A and 10B is possible to perform communication through the I/O device 17 of the system of the CPU 12 of the system and a routing element 14. The communication between the I/O device 17 operating in a simplex mode and the CPUs 12 is performed by the message made into a packet. The CPUs 12 and the I/O device are written in the memory of the CPU 12 of the system or are read from the memory. The protection of the memory is maintained by each CPU 12 provided with the propriety inspection for the reading/writing to the memory of the CPU 12.

公开(公告)号：JPH09138774A

公开(公告)日：1997-05-27

申请号：JP14573496

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO ,  UIRIAMU JIYOERU WATOSON ,  DEIBUITSUDO POORU SOONIA

IPC: G06F7/507 ,  G06F7/508 ,  G06F11/18 ,  G06F13/14 ,  G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  H04L12/56 ,  G06F7/50 ,  G06F15/173

Abstract: PROBLEM TO BE SOLVED: To attain the arbitration that instantaneously uses a mechanism of high priority by monitoring the message traffic passing through every port input and elevating the priority of the port input having the message traffic under waiting. SOLUTION: A multiprocess system 10 includes at least a pair of CPUs 12a and 12b, a route designation unit, i.e., a router 16, and plural input/output units 14a to 14i which are connected to each other in a system area network constitution via a two-way communication link 18. When the two-level arbitration is carried out, the arbitration is first given between two port inputs which acquire the port input accesses by means of a low level priority mechanism. Then the port inputs having the message traffic under waiting are accepted through many arbitration cycles. Thus the priority levels of these port inputs are elevated, and the arbitration using instantaneously a high priority mechanism is applied.

公开(公告)号：JPH09134333A

公开(公告)日：1997-05-20

申请号：JP14527196

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO

IPC: G06F12/16 ,  G06F1/04 ,  G06F11/18 ,  G06F12/08 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To provide a multiprocessor system via a simple system by attaining a fault tolerant action through the fail-first and fail-functional actions. SOLUTION: This clock circuit includes a binary input counter and a binary output counter and deletes the data elements out of plural storage positions of an FIFO. A clock generator supplies a clock signal of frequency F1 having an N-to-M ratio (N, M: integers and N>M) against the frequency Fo of a received clock signal. A serial shift register has plural continuous register stages to receive the clock signals from the clock generator and shifts the data bits which are received at these register stages. Then a multiplexer selectively receives one of register stages in response to a control signal and forms a sub-shift register which has plural shift registers.

公开(公告)号：JPH09128355A

公开(公告)日：1997-05-16

申请号：JP14525196

申请日：1996-06-07

Applicant: TANDEM COMPUTERS INC

Inventor： ROBAATO DABURIYUU HOOSUTO

IPC: G06F11/18 ,  G01R31/317 ,  G01R31/3185 ,  G06F1/12 ,  G06F9/52 ,  G06F11/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/20 ,  G06F11/273 ,  G06F12/08 ,  G06F12/14 ,  G06F12/16 ,  G06F13/00 ,  H04L12/56 ,  H04L29/14 ,  G06F15/16

Abstract: PROBLEM TO BE SOLVED: To obtain s useful tool for fault separation by providing an error inspecting function, and detecting and processing a difference (divergence) between two CPUs which operate in duplex mode. SOLUTION: A data processing system 10 is equipped with two subprocessor systems 10A and 10B which have substantially the same structure and functions. Each of the subprocessor systems 10A and 10B includes a central processing unit(CPU) 12, a router 14, and an I/O packet interface 16 having a relative I/O 17. The pair of CPUs 12 operate at the same time to copy the same instruction in an instruction stream and the instruction stream at substantially the same time and perform substantially the same operation at substantially the same time, thereby supplying output data. Here, a data inspecting element is used to receive the output data from the couple of CPUs 12 and compare the data with each other.

公开(公告)号：JPH09116570A

公开(公告)日：1997-05-02

申请号：JP14320096

申请日：1996-06-05

Applicant: TANDEM COMPUTERS INC

Inventor： JIYON SHII KURAUSU ,  UIRIAMU JIYOERU WATOSON ,  DEIBUITSUDO POORU SOONIA ,  ROBAATO DABURIYUU HOOSUTO

IPC: G06F13/14 ,  G06F13/40 ,  H04L12/56 ,  H04L12/46 ,  H04L12/28 ,  H04L12/44 ,  H04L12/66

Abstract: PROBLEM TO BE SOLVED: To provide a method of providing a bias to decide any of two or more inputs in contention with respect to a data communication access to the same output. SOLUTION: A designated bias value is given to each input of a router 16 allowing one communication, cumulated bias values are generated and the resulting input is compared with other inputs decided for access to its output. One of the inputs is selected for the output access based on the comparison and the cumulated bias value of the selected input is decreased by the sum of designated bias values of the other inputs participating the decision but not selected. On the other hand, each of the cumulated bias values of the other inputs taking part in the decision is increased by the designated bias value corresponding thereto. Thus, the expectation to the output access is higher for lots of the going to access the same output as they are kept waiting for a longer time, and conversely the input allowed for the access has less expectation to the access just after the allowed access in order to allow the access by the other inputs.