公开(公告)号：US10950687B2

公开(公告)日：2021-03-16

申请号：US16874691

申请日：2020-05-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/15 ,  H01L49/02 ,  H01L23/498

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.

公开(公告)号：US20210076508A1

公开(公告)日：2021-03-11

申请号：US16950910

申请日：2020-11-18

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Fu-Yang Chen ,  Ra-Min Tain

IPC: H05K3/46 ,  H05K3/40 ,  H05K3/42 ,  H05K3/28 ,  H05K3/30 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00

Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

公开(公告)号：US10888001B2

公开(公告)日：2021-01-05

申请号：US16244113

申请日：2019-01-10

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Fu-Yang Chen ,  Ra-Min Tain

IPC: H05K7/10 ,  H05K3/46 ,  H05K3/40 ,  H05K3/42 ,  H05K3/28 ,  H05K3/30 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00

Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

公开(公告)号：US20200273948A1

公开(公告)日：2020-08-27

申请号：US16874691

申请日：2020-05-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/498 ,  H01L23/532 ,  H01L23/15

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure.

公开(公告)号：US10700161B2

公开(公告)日：2020-06-30

申请号：US16159726

申请日：2018-10-15

Applicant: Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Fu-Yang Chen ,  Chun-Hsien Chien ,  Chien-Chou Chen ,  Wei-Ti Lin

IPC: H01L49/02 ,  H01L23/522 ,  H01L23/498 ,  H01L23/15 ,  H01L23/532

Abstract: A manufacturing method of a substrate structure includes the following steps. A first build-up circuit structure is formed. At least one copper pillar is formed on the first build-up circuit structure. A dielectric layer is formed on the first build-up circuit structure, and the dielectric layer wraps the copper pillar. A second build-up circuit structure and a capacitive element are formed on the dielectric layer. In particular, the second build-up circuit structure and the first build-up circuit structure are respectively located at two opposite sides of the dielectric layer. The capacitive element is disposed in a capacitive element setting region within the second build-up circuit structure. The copper pillar penetrates the dielectric layer and is electrically connected to the second build-up circuit structure and the first build-up circuit structure. A substrate structure obtained by the manufacturing method of the substrate structure is provided.

公开(公告)号：US09860980B1

公开(公告)日：2018-01-02

申请号：US15273672

申请日：2016-09-22

Applicant: Unimicron Technology Corp.

Inventor： Yu-Chung Hsieh ,  Chun-Hsien Chien ,  Wei-Ti Lin ,  Yu-Hua Chen

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0306 ,  H05K1/0271 ,  H05K3/0052 ,  H05K3/4605 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/068 ,  H05K2201/09845

Abstract: A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.