公开(公告)号：TWI503953B

公开(公告)日：2015-10-11

申请号：TW102133139

申请日：2013-09-13

Applicant: 台灣積體電路製造股份有限公司 ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： 朱家驊 ,  CHU, CHIA HUA ,  鄭鈞文 ,  CHENG, CHUN WEN ,  李德浩 ,  LEE, TE HAO ,  林宗賢 ,  LIN, CHUNG HSIEN

IPC: H01L27/04 ,  H01L23/12

CPC classification number: B81B7/0064 ,  B81B2203/04 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00238 ,  B81C2201/014 ,  B81C2203/0792 ,  H01L24/18 ,  H01L29/84 ,  H01L2924/01322 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/00

公开(公告)号：TW201014780A

公开(公告)日：2010-04-16

申请号：TW097137955

申请日：2008-10-02

Applicant: 財團法人工業技術研究院

Inventor： 陳振頤 ,  王欽宏

IPC: B81B ,  B81C

CPC classification number: B81C1/00476 ,  B81B2201/0257 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2203/0714 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00

Abstract: 一種微機電結構及其製造方法，其中的微機電結構包括一個基板以及位在基板上的至少一個懸空微結構。前述懸空微結構包括多層金屬層、至少一層介電層以及至少一邊緣金屬壁。其中，介電層被夾在金屬層之間，而邊緣金屬壁則平行於懸空微結構的厚度方向並圍繞介電層的邊緣。上述邊緣金屬壁可阻擋製程中的蝕刻液蝕刻介電層，而金屬層複合介電層之結構則可以增加懸空微結構在厚度方向上的結構強度。

Abstract in simplified Chinese: 一种微机电结构及其制造方法，其中的微机电结构包括一个基板以及位在基板上的至少一个悬空微结构。前述悬空微结构包括多层金属层、至少一层介电层以及至少一边缘金属壁。其中，介电层被夹在金属层之间，而边缘金属壁则平行于悬空微结构的厚度方向并围绕介电层的边缘。上述边缘金属壁可阻挡制程中的蚀刻液蚀刻介电层，而金属层复合介电层之结构则可以增加悬空微结构在厚度方向上的结构强度。

公开(公告)号：TW200732244A

公开(公告)日：2007-09-01

申请号：TW096101925

申请日：2007-01-18

Applicant: 高通微機電系統科技公司 QUALCOMM MEMS TECHNOLOGIES, INC.

Inventor： 張萬宿 CHUNG, WONSUK ,  史帝夫 季 ZEE, STEVE ,  照夫川 SASAGAWA, TERUO

IPC: B81B ,  H01L ,  G02F

CPC classification number: B81C1/00801 ,  B81B2201/047 ,  B81C2201/014 ,  G02B26/001 ,  Y10T428/31678

Abstract: 藉由於一犧牲層與一電極14a、14b、14c之間使用一蝕刻停止層104b,改良一諸如干涉調變器之微機電系統(MEMS)裝置之製造。蝕刻停止層104b可減少該犧牲層及該電極14a、14b、14c之不當的過分蝕刻。蝕刻停止層104b亦可充當一障壁層、緩衝層及/或模板層。該蝕刻停止層104b可包括富含矽之氮化矽。

Abstract in simplified Chinese: 借由于一牺牲层与一电极14a、14b、14c之间使用一蚀刻停止层104b,改良一诸如干涉调制器之微机电系统(MEMS)设备之制造。蚀刻停止层104b可减少该牺牲层及该电极14a、14b、14c之不当的过分蚀刻。蚀刻停止层104b亦可充当一障壁层、缓冲层及/或模板层。该蚀刻停止层104b可包括富含硅之氮化硅。

公开(公告)号：US20240158225A1

公开(公告)日：2024-05-16

申请号：US18075882

申请日：2022-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jung-Hao CHANG ,  Weng-Yi CHEN

IPC: B81C1/00 ,  B81B7/02

CPC classification number: B81C1/00476 ,  B81B7/02 ,  B81B2201/0257 ,  B81B2203/0315 ,  B81B2203/033 ,  B81B2203/0353 ,  B81B2207/01 ,  B81C2201/0108 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  B81C2201/0176

Abstract: A micro electro mechanical system (MEMS) device and a method for manufacturing the same are provided. The MEMS device includes a substrate, a polymer film on the substrate and having a lower surface facing toward the substrate, a cavity passing through the substrate, and coil structures on the substrate and in the polymer film. The polymer film includes a corrugation pattern on the lower surface of the polymer film. A portion of the polymer film is exposed in the cavity.

公开(公告)号：US20230416079A1

公开(公告)日：2023-12-28

申请号：US18337942

申请日：2023-06-20

Applicant: Robert Bosch GmbH

Inventor： Heribert Weber ,  Peter Schmollngruber

IPC: B81B7/02 ,  B81C1/00 ,  G01L1/22

CPC classification number: B81B7/02 ,  B81C1/00166 ,  G01L1/2262 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0307 ,  B81B2203/0315 ,  B81B2203/04 ,  B81C2201/014

Abstract: A micromechanical component for a sensor and/or microphone device. The component has an adjustable first actuator electrode suspended on a regionally deformable first layer, a first stator electrode fastened so that a first measuring signal is able to be tapped with regard to a first voltage or capacitance applied between the first actuator electrode and the first stator electrode, and a second actuator electrode, so that a second measuring signal is able to be tapped with regard to a second voltage or capacitance applied between the second actuator electrode and the first stator electrode or between the second actuator electrode and the second stator electrode. The second actuator electrode is situated in an adjustable manner on a side of the first actuator electrode facing away from the first layer in that the second actuator electrode is suspended on the first actuator electrode and/or an at least regionally deformable second layer.

公开(公告)号：US20230348258A1

公开(公告)日：2023-11-02

申请号：US18302610

申请日：2023-04-18

Applicant: STMicroelectronics S.r.l.

Inventor： Mikel AZPEITIA URQUIA ,  Enri DUQI ,  Silvia NICOLI ,  Roberto CAMPEDELLI ,  Igor VARISCO ,  Lorenzo TENTORI

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81C1/00158 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/033 ,  B81B2203/0361 ,  B81B2207/11 ,  B81C2201/014 ,  B81C2201/0156 ,  B81C2201/0177 ,  B81C2201/0169

Abstract: MEMS structure, comprising: a semiconductor body; a cavity buried in the semiconductor body; a membrane suspended on the cavity; and at least one antistiction bump completely contained in the cavity with the function of preventing the side of the membrane internal to the cavity from sticking to the opposite side, which delimits the cavity downwardly.

公开(公告)号：US20230202835A1

公开(公告)日：2023-06-29

申请号：US18115178

申请日：2023-02-28

Applicant: InvenSense, Inc.

Inventor： Daesung Lee ,  Alan Cuthbertson

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00095 ,  B81B7/0006 ,  B81B2207/07 ,  B81B2207/012 ,  B81C2201/014 ,  B81C2201/0198 ,  B81C2203/036 ,  B81C2203/0792

Abstract: A method including fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a hardmask on a second side of the device wafer, wherein the second side is planar. An etch stop layer is deposited over the hardmask and an exposed portion of the second side of the device wafer. A dielectric layer is formed over the etch stop layer. A via is formed within the dielectric layer. The via is filled with conductive material. A eutectic bond layer is formed over the conductive material. Portions of the dielectric layer uncovered by the eutectic bond layer is etched to expose the etch stop layer. The exposed portions of the etch stop layer is etched. A micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

公开(公告)号：US20180208460A1

公开(公告)日：2018-07-26

申请号：US15448804

申请日：2017-03-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Huang Chiu ,  Weng-Yi Chen ,  Kuan-Yu Wang

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00246 ,  B81B7/0006 ,  B81B2201/0214 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/0384 ,  B81B2203/0392 ,  B81B2203/04 ,  B81C2201/014 ,  B81C2203/0735 ,  B81C2203/0771

Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a MEMS region. The MEMS region includes a sensing membrane and a metal ring. The metal ring defines a cavity under the sensing membrane.

公开(公告)号：US20180086627A1

公开(公告)日：2018-03-29

申请号：US15573342

申请日：2015-06-22

Applicant: Intel Corporation

Inventor： Kevin LAI LIN ,  Chytra PAWASHE ,  Raseong KIM ,  Ian A. YOUNG ,  Kanwal Jit SINGH ,  Robert L. BRISTOL

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/07 ,  B81B2207/092 ,  B81B2207/094 ,  B81B2207/095 ,  B81C1/00246 ,  B81C1/00301 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2203/0714 ,  B81C2203/0742 ,  B81C2203/0771 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829

Abstract: A conductive layer is deposited into a trench in a sacrificial layer on a substrate. An etch stop layer is deposited over the conductive layer. The sacrificial layer is removed to form a gap. In one embodiment, a beam is over a substrate. An interconnect is on the beam. An etch stop layer is over the beam. A gap is between the beam and the etch stop layer.

公开(公告)号：US20170297896A1

公开(公告)日：2017-10-19

申请号：US15291374

申请日：2016-10-12

Applicant: Robert Bosch GmbH

Inventor： Andrew Graham ,  Gary Yama ,  Gary O'Brien

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0021 ,  B81B2201/0271 ,  B81B2203/04 ,  B81B2203/053 ,  B81C1/00095 ,  B81C1/00166 ,  B81C2201/0132 ,  B81C2201/014 ,  B81C2201/0177 ,  B81C2203/0136

Abstract: A device with an out-of-plane electrode includes a device layer positioned above a handle layer, a first electrode defined within the device layer, a cap layer having a first cap layer portion spaced apart from an upper surface of the device layer by a gap, and having an etch stop perimeter defining portion defining a lateral edge of the gap, and an out-of-plane electrode defined within the first cap layer portion by a spacer.