公开(公告)号：EP2166656B1

公开(公告)日：2013-04-10

申请号：EP08425608.0

申请日：2008-09-18

Applicant: STMicroelectronics Srl

Inventor： Conte, Antonino ,  Ucciardello, Carmelo ,  Matranga, Giovanni

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/077

公开(公告)号：EP1873837B1

公开(公告)日：2013-03-27

申请号：EP06425448.5

申请日：2006-06-28

Applicant: STMicroelectronics Srl

Inventor： Saggio, Mario Giuseppe ,  Murabito, Domenico ,  Frisina, Ferruccio

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L21/329 ,  H01L21/336 ,  H01L29/417 ,  H01L29/08 ,  H01L21/20 ,  H01L21/324 ,  H01L29/739 ,  H01L29/872 ,  H01L29/732

CPC classification number: H01L29/7811 ,  H01L21/324 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/66128 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A process for manufacturing a semiconductor power device envisages the steps of: providing a body (3) made of semiconductor material having a first top surface (3a); forming an active region (4a; 29, 30) with a first type of conductivity in the proximity of the first top surface (3a) and inside an active portion (1a) of the body (3); and forming an edge-termination structure (4b, 5). The edge-termination structure is formed by: a ring region (5) having the first type of conductivity and a first doping level, set within a peripheral edge portion (1b) of the body (3) and electrically connected to the active region; and a guard region (4b), having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface (3a) and connecting the active region (4a; 29, 30) to the ring region (5). The process further envisages the steps of: forming a surface layer (9) having the first type of conductivity on the first top surface (3a), also at the peripheral edge portion (1b), in contact with the guard region; and etching the surface layer (9) in order to remove it above the edge portion (1b) in such a manner that the etch terminates inside the guard region (4b).

公开(公告)号：EP2075708B1

公开(公告)日：2013-02-13

申请号：EP08022446.2

申请日：2008-12-24

Applicant: STMicroelectronics Srl

Inventor： Ciccarelli, Luca ,  Canegallo, Roberto ,  Magagni, Luca ,  Fazzi, Alberto ,  Guerrieri, Roberto

IPC: G06F13/40 ,  H04L7/00

CPC classification number: G06F13/4077 ,  H04L25/0266 ,  H04L25/028

公开(公告)号：EP2290784A3

公开(公告)日：2012-12-19

申请号：EP10166273.2

申请日：2010-06-17

Applicant: STMicroelectronics Srl

Inventor： Ruà, Francesco ,  Privitera, Salvatore Giuseppe ,  Signorelli, Tiziana Teresa ,  Pulvirenti, Francesco

IPC: H02J7/35 ,  G05F1/67

CPC classification number: H02J7/35 ,  Y02E10/566 ,  Y02E10/58 ,  Y10T307/593

Abstract: An outstandingly effective method of maximum power point tracking (MPPT) in operating a photovoltaic power plant that includes at least a DC-DC converter of the output voltage ( V PV ) of a single panel or of a plurality of series-parallel interconnected panels, having a power switch driven by a PWM control signal ( V PWM ) of variable duty-cycle (D) generated by a PWM control circuit, in discontinuous conduction mode (DCM) or continuous conduction mode (CCM) depending on the current load of the converter, is implemented by simple low cost analog circuits. The method does not require the use of any analog to digital conversion, digital processing or storage resources and requires only a single voltage sensor, in other words, no dissipative sensing resistance needs to be introduced.

公开(公告)号：EP1511042B1

公开(公告)日：2012-12-05

申请号：EP03077667.8

申请日：2003-08-27

Applicant: STMicroelectronics Srl

Inventor： Bedeschi, Ferdinando ,  Resta, Claudio

IPC: G11C13/00 ,  G11C7/12

CPC classification number: G11C7/12 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2213/79

公开(公告)号：EP2515442A1

公开(公告)日：2012-10-24

申请号：EP11425111.9

申请日：2011-04-21

Applicant: STMicroelectronics SA ,  STMicroelectronics Srl ,  L'Université de Monastir

Inventor： Zid, Mounir ,  Scandurra, Alberto ,  Pistritto, Carmelo ,  Tourki, Rached

IPC: H03M9/00

CPC classification number: H03M9/00

Abstract: An arrangement comprises an input configured to receive data; and at least one multiplexer configured to receive a first logic level at a first input and a second logic level at a second level, at least a part of said data being received at a control input of said multiplexer.

Abstract translation: 一种配置包括被配置为接收数据的输入; 以及至少一个多路复用器，被配置为在第一输入端接收第一逻辑电平并且在第二电平接收第二逻辑电平，所述数据的至少一部分在所述多路复用器的控制输入端被接收。

公开(公告)号：EP2515226A1

公开(公告)日：2012-10-24

申请号：EP11425113.5

申请日：2011-04-21

Applicant: STMicroelectronics SA ,  STMicroelectronics Srl

Inventor： Zid, Mounir ,  Scandurra, Alberto

IPC: G06F5/08

CPC classification number: G06F5/08

Abstract: An arrangement comprising a plurality of data stores, each data store being configured to store data, and a controller arranged to selectively apply a clock signal to said respective data stores.

Abstract translation: 一种包括多个数据存储器的装置，每个数据存储器被配置为存储数据，以及控制器，被布置为选择性地将时钟信号应用于所述各个数据存储器。

公开(公告)号：EP2515197A1

公开(公告)日：2012-10-24

申请号：EP11425114.3

申请日：2011-04-21

Applicant: STMicroelectronics SA ,  STMicroelectronics Srl

Inventor： Zid, Mounir ,  Scandurra, Alberto

IPC: G06F1/04

CPC classification number: G06F1/04 ,  G06F1/10

Abstract: A circuit comprises a first Muller gate having a first input configured to receive a clock signal, a second input configured to receive an enable signal and an output. A logic circuit is also provided having a first input configured to receive said clock signal, and a second input configured to receive an input dependent on said output, said logic circuit being configured to provide a gated clock output.

Abstract translation: 电路包括具有被配置为接收时钟信号的第一输入的第一穆勒门，被配置为接收使能信号和输出的第二输入。 还提供了具有被配置为接收所述时钟信号的第一输入的逻辑电路，以及被配置为接收依赖于所述输出的输入的第二输入，所述逻辑电路被配置为提供门控时钟输出。

公开(公告)号：EP2367315B1

公开(公告)日：2012-10-17

申请号：EP11155057.0

申请日：2011-02-18

Applicant: STMicroelectronics Srl

Inventor： Condorelli, Riccardo ,  Carrano, Michele Alessandro

IPC: H04L7/00

CPC classification number: H04L7/02 ,  H04L7/0045

公开(公告)号：EP2317637B1

公开(公告)日：2012-09-12

申请号：EP10191502.3

申请日：2001-10-19

Applicant: STMicroelectronics Srl

Inventor： Milazzotto, Antonino ,  Di Guardo, Mario ,  Cucuccio, Antonino ,  Di Marco, Francesco

IPC: H02M5/293

CPC classification number: H02M5/293