中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

278 records (took 0.026 seconds)

    Tray
    32.
    发明授权
    Tray 有权

    公开(公告)号：US11764090B2

    公开(公告)日：2023-09-19

    申请号：US17690121

    申请日：2022-03-09

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Hsu-Chi Lee ,  Pi-Yu Peng ,  Chun-Te Lee

    IPC: H01L21/673

    CPC classification number: H01L21/67333

    Abstract: A tray includes a body for placement of a component (e.g. electronic component) and a taker disposed on a bottom surface of the body. The taker is used to take a spacer and includes a first taking element and a second taking element. The first taking element includes a first connection portion and a first confinement portion, and the second taking element includes a second connection portion and a second confinement portion. An accommodation space is provided between the first and second connection portions and a passageway is provided between the first and second confinement portions. While the spacer is moved through the passageway and into the accommodation space, it is confined in the accommodation space by the first and second confinement portions such that the taker can take away the spacer to show another tray located under the spacer as the tray is removed.

    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    33.
    发明公开
    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20230170301A1

    公开(公告)日：2023-06-01

    申请号：US17972648

    申请日：2022-10-25

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Chin-Tang Hsieh ,  You-Ming Hsu ,  Chun-Ting Kuo ,  Lung-Hua Ho ,  Chih-Ming Kuo

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/552

    CPC classification number: H01L23/5286 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/552

    Abstract: A semiconductor structure includes a substrate, a dielectric layer, a connection layer and wire layers. The dielectric layer is disposed on a surface of the substrate and includes vias showing the surface. The connection layer is disposed on the dielectric layer, a first connection portion of the connection layer is located in the vias and connected to the surface, a second connection portion of the connection layer is connected to the dielectric layer. A first ground portion of the ground metal layer is connected to the first connection portion of the connection layer, and a second ground portion of the ground metal layer is connected to the second connection portion of the connection layer. Each of the wire layers is disposed on the second connection portion of the connection layer, and the second ground portion is located between the adjacent wire layers.

    Surface acoustic wave device and method of manufacturing the same
    34.
    发明授权
    Surface acoustic wave device and method of manufacturing the same 有权

    公开(公告)号：US11522517B2

    公开(公告)日：2022-12-06

    申请号：US16581901

    申请日：2019-09-25

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Cheng-Hung Shih ,  Cheng-Fan Lin

    IPC: H03H9/02 ,  H01L41/047 ,  H03H9/05 ,  H03H9/145

    Abstract: A surface acoustic wave device includes a piezoelectric substrate, a supportive layer, a cover layer and a pillar bump. The supportive layer is disposed on the piezoelectric substrate and around a transducer, the cover layer covers the supportive layer, and the pillar bump is located in a lower via hole of the supportive layer and an upper via hole of the cover layer. The upper via hole has a lateral opening located on a lateral surface of the cover layer, and the pillar bump in the cover layer protrudes from the lateral surface of the cover layer via the lateral opening.

    CIRCUIT BOARD TAPE AND JOINING METHOD THEREOF
    36.
    发明申请
    CIRCUIT BOARD TAPE AND JOINING METHOD THEREOF 有权

    公开(公告)号：US20220087017A1

    公开(公告)日：2022-03-17

    申请号：US17380121

    申请日：2021-07-20

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Yin-Chen Lin ,  Ming-Hsiao Ke ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

    IPC: H05K1/03 ,  H05K13/04 ,  H05K13/02

    Abstract: A circuit board tape includes substrate units each including a sprocket-hole region, a layout region and a joining mark. There are odd and more than three sprocket holes on the sprocket-hole region. An imaginary line extended from the joining mark is extended to between a first layout and a second layout located on the layout region. The amount of the sprocket holes between the imaginary lines of the adjacent substrate units is odd. The circuit board tape is cut along the imaginary lines of the different substrate units so as to remove the defective substrate unit from the circuit board tape and divide the circuit board tape into a front tape and a rear tape. After joining the front and rear tapes, the region where a first layout on the front tape and a second layout on the rear tape are located is defined as a combined layout region.

    FLIP CHIP INTERCONNECTION AND CIRCUIT BOARD THEREOF
    38.
    发明申请
    FLIP CHIP INTERCONNECTION AND CIRCUIT BOARD THEREOF 有权

    公开(公告)号：US20210202422A1

    公开(公告)日：2021-07-01

    申请号：US16910461

    申请日：2020-06-24

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Yu-Chen Ma ,  Hsin-Hao Huang ,  Wen-Fu Chou ,  Gwo-Shyan Sheu

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538

    Abstract: A flip chip interconnection includes a circuit board, a chip and a solder layer. The chip is mounted on an inner bonding area of the circuit board, the solder layer is located between the circuit board and the chip for bonding bumps to inner leads and a T-shaped circuit unit on the inner bonding area. The T-shaped circuit unit has a main part, a connection part and a branch part, the connection part is connected to the main and branch parts, respectively. The main part extends along a lateral direction and the branch part extends outwardly along a longitudinal direction. The connection part is narrower than the main part in width so as to prevent solder short caused by solder overflow on the branch part.

    CIRCUIT BOARD
    39.
    发明申请
    CIRCUIT BOARD 有权

    公开(公告)号：US20210185800A1

    公开(公告)日：2021-06-17

    申请号：US16866796

    申请日：2020-05-05

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Yi-Chen Lien ,  Yen-Ping Huang ,  Hui-Yu Huang ,  Chih-Ming Peng ,  Chun-Te Lee

    IPC: H05K1/02 ,  H05K3/00

    Abstract: A circuit board includes a substrate having a through hole, a circuit layer, a first measurement mark and a second measurement mark. According to the first and second measurement marks, an electronic detection device can measure a first distance between a first edge of the through hole and the first measurement mark and a second distance between a second edge of the through hole and the second measurement mark to determine whether the through hole has an undesired size or shift.

    Chip package and chip thereof
    40.
    发明授权
    Chip package and chip thereof 有权

    公开(公告)号：US10797213B2

    公开(公告)日：2020-10-06

    申请号：US16260528

    申请日：2019-01-29

    Applicant: CHIPBOND TECHNOLOGY CORPORATION

    Inventor： Chin-Tang Hsieh ,  Cheng-Hung Shih

    IPC: H01L33/62 ,  H01L33/38

    Abstract: A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

Patent Agency Ranking