PROCESSOR ARCHITECTURE SCHEME
    31.
    发明专利

    公开(公告)号:JPH11224193A

    公开(公告)日:1999-08-17

    申请号:JP28565798

    申请日:1998-10-07

    Abstract: PROBLEM TO BE SOLVED: To make selectable an addressing mode for every instruction by establishing a virtual register address set equivalent to many indirect addressing modes relating to an indirect addressing pointer inside a memory. SOLUTION: A data pointer register requires respective virtual register address positions inside a data memory for the respective indirect addressing modes desiring the realization of data pointer registers. The respective data pointer registers are provided with one or more reserved virtual register address positions inside a register address map. When the respective reserved virtual register address positions are accessed, the indirect addressing mode to the corresponding data pointer register is started. For instance, the respective data pointer registers which are the pointers of a 12-bit width capable of accessing the memory area of the length of 4K bytes are constituted as two 8-bit width registers accessible as readable and writable registers.

    FORCED PAGE PAGING SYSTEM FOR MICROCONTROLLERS WITH VARIOUS SIZE TO USE DATA RANDOM ACCESS MEMORY

    公开(公告)号:JP2001249845A

    公开(公告)日:2001-09-14

    申请号:JP2001044208

    申请日:2001-02-20

    Inventor: YACH RANDY L

    Abstract: PROBLEM TO BE SOLVED: To provide improved microcontroller structure and a paging system not to increase the size of a microcontroller. SOLUTION: This paging system includes a process to linearize the entire address area of a random access memory, a process to divide the linearized address area of the random access memory into plural pages and in which each of the plural pages is selected from a group with size of 256 bytes and 64 K bytes, a process to use the pages of the random access memory exclusive for special and multi-purpose registers and a process not to affect the present operation of the microcomputer and not to change the presently selected address stored in a page selection register which is used by the microcomputer when the microcomputer is set so that forced data access is generated by the exclusive pages.

    MICROCONTROLLER FOR PERFORMING CORE LOGIC POWER SHUT- DOWN WHILE KEEPING COMPLETENESS OF INPUT/OUTPUT PORT

    公开(公告)号:JP2001184330A

    公开(公告)日:2001-07-06

    申请号:JP2000336638

    申请日:2000-11-02

    Abstract: PROBLEM TO BE SOLVED: To provide a system, a method and a device for maintaining a control and/or status state while keeping power in an integrated circuit(IC) microcontroller. SOLUTION: A microcontroller IC 100 is provided with a microcontroller core logic 102, an input/output port logic 106 suited to the storage of an output logic level, an interface logic 104 connected between the microcontroller core logic 102 and the input/output port logic 106, and a power switch 110 connected to the microcontroller core logic 102. When a power source 108 is connected to the microcontroller core logic 102, the microcontroller core logic 102 controls the output logic level of the input/output port logic 106 and when the power source 108 is disconnected from the microcontroller core logic 102, the output logic level of the input/output port logic 106 maintains the same state as just before the disconnection of the power source 108 from the microcontroller core logic 102.

    DEVICE AND METHOD FOR RESETTING PIN ALLOCATION IN ONE OR MORE FUNCTION CIRCUITS IN MICROCONTROLLER

    公开(公告)号:JP2000330968A

    公开(公告)日:2000-11-30

    申请号:JP2000108694

    申请日:2000-04-10

    Abstract: PROBLEM TO BE SOLVED: To simultaneously use two pieces of different peripheral equipment capable of functioning by a single pin by providing process circuit mechanism and settable pin setting. SOLUTION: A multiplexer 14 is connected with a function circuit 12 via a communication line 18, connected with a pin P1 via a communication line 20, connected with a pin P2 via a communication line 22 and connected with a setting register 16 via a communication line 24. When a flag received from the setting register 16 is '1', the multiplexer 14 is operated so as to connect the function circuit 12 with the pin P1. When the flag received from the setting register 16 is 'zero', the multiplexer 14 is further operated so as to connect the function circuit 12 with the pin P2. Therefore, a user is able to transfer a function related to the function circuit 12 from one pin to another by using the multiplexer 14 and the setting register 16 by a circuit 10.

    IMPROVED INTEGRATED CIRCUIT TRANSPONDER AND COMMUNICATION METHOD THEREFOR

    公开(公告)号:JPH11243350A

    公开(公告)日:1999-09-07

    申请号:JP28566998

    申请日:1998-10-07

    Abstract: PROBLEM TO BE SOLVED: To enable a reader to detect gap in an electromagnetic field regardless of a chip ground signal by providing a detecting means that detects a time when the voltage of each end part of a coil is almost equal over a certain period. SOLUTION: A tag 10 includes a single package that seals an IC semiconductor chip, a coil 14 that is selectively exposed to an electromagnetic field 12 in the package and a detecting part which exists on the IC semiconductor chip, is connected to each end part of the coil 14 and detects voltage when the voltage of each end part of the coil 14 is almost equal over a prescribed period. A reader is designed to transmit the field 12 and to pass through the coil 14 and selective interruption or gap in transmission in the field 12 is detected by the tag 10. Coil voltage having a resonance frequency that is the result of the inductance value of the coil 14 and the capacitive value of a capacitor 16 is introduced by such a manner that the field 12 passes through the coil 14.

    ROBUST MULTIPLE WORD INSTRUCTION AND ITS METHOD

    公开(公告)号:JPH11191066A

    公开(公告)日:1999-07-13

    申请号:JP27616598

    申请日:1998-09-29

    Abstract: PROBLEM TO BE SOLVED: To obtain an instruction set that is improved by a microcontroller by arranging one bit of a multiple work instruction of an instruction set at a position in the entire non-leading word and decoding it as no operation bit when a leading word of the multiple word instruction is not first carried out. SOLUTION: In each multiple work instruction 2 and 3, at least one no- operation bit 18 is arranged at a prescribed position in each non-leading word 14B to 14N. When a leading word 14A is not executed before a word that follows it in a multiple word instruction, each non-leading word 14B to 14N of the multiple word instructions is recognized as a non-operation word by the bit 18. Then, in an instruction 3, if the word 14A is not carried out before a 2nd word 14B or N-th word 14N when a microcontroller jumps in the word 14B or the word 14N in the instruction carelessly, the microcontroller decodes each non-leading word 14B to 14N as no operation word.

Patent Agency Ranking