公开(公告)号：US6432789B2

公开(公告)日：2002-08-13

申请号：US72693900

申请日：2000-11-30

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： GRIS YVON

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/732

CPC classification number: H01L29/0804 ,  H01L29/1004

Abstract: The present invention relates to an integrated circuit including a lateral well isolation bipolar transistor. A first portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor base, to form a base contacting region. A second portion of the upper internal periphery of the insulating well is hollowed and filled with polysilicon having the same conductivity type as the transistor emitter, to form an emitter contacting region.

Abstract translation: 本发明涉及一种包括横向阱隔离双极晶体管的集成电路。 绝缘阱的上部内周的第一部分是中空的，并且填充有与晶体管基底相同导电类型的多晶硅，以形成基极接触区域。 绝缘阱的上部内周的第二部分是中空的，并且填充与晶体管发射极具有相同导电类型的多晶硅，以形成发射极接触区域。

公开(公告)号：US20020078330A1

公开(公告)日：2002-06-20

申请号：US09842312

申请日：2001-04-25

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Andrew C. Sturges ,  Nathan M. Sidwell

IPC: G06F009/00

CPC classification number: G06F9/3804 ,  G06F9/3842

Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

Abstract translation: 描述用于执行分支指令的计算机系统和执行分支指令的方法。 两个指令取出器分别从存储器执行的指令序列和从执行的指令序列中的由设置的分支指令识别的目标位置开始的指令序列。 当产生效果分支信号时，接下来执行目标指令，并且获取执行指令的获取器开始获取目标指令。 效果分支信号与设定的分支指令分开产生。 在另一方面，效果分支信号是在执行位于要采用分支的指令序列中的点处的条件效果分支指令时产生的。

公开(公告)号：US20020002657A1

公开(公告)日：2002-01-03

申请号：US09924289

申请日：2001-08-08

Applicant: SGS-Thomson Microelectronics Limited

Inventor： Andrew C. Sturges ,  David May

IPC: G06F012/00

CPC classification number: G06F12/126 ,  G06F12/0842 ,  G06F12/0848 ,  G06F12/0864 ,  G06F12/0888

Abstract: A method of operating a cache memory is described in a system in which a processor is capable of executing a plurality of processes, each process including a sequence of instructions. In the method a cache memory is divided into cache partitions, each cache partition having a plurality of addressable storage locations for holding items in the cache memory. A partition indicator is allocated to each process identifying which, if any, of said cache partitions is to be used for holding items for use in the execution of that process. When the processor requests an item from main memory during execution of said current process and that item is not held in the cache memory, the item is fetched from main memory and loaded into one of the plurality of addressable storage locations in the identified cache partition.

Abstract translation: 在其中处理器能够执行多个处理的系统中描述了操作高速缓冲存储器的方法，每个处理包括一系列指令。 在该方法中，高速缓冲存储器被分为高速缓存分区，每个高速缓存分区具有多个可寻址存储位置，用于保存高速缓冲存储器中的项目。 分配指示符被分配给每个进程，标识哪个（如果有的话）所述高速缓存分区将用于保存用于执行该进程的项目。 当处理器在执行所述当前进程期间请求来自主存储器的项目并且该项目不被保存在高速缓冲存储器中时，该项目从主存储器中取出并被加载到所识别的高速缓存分区中的多个可寻址存储位置之一中。

公开(公告)号：US5795800B1

公开(公告)日：2000-03-28

申请号：US68639596

申请日：1996-07-25

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： CHAN TSIU CHIU ,  BALASINSKI ARTUR P

IPC: H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L27/12 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L27/1203 ,  H01L27/0921 ,  H01L27/0922 ,  H01L27/1104

公开(公告)号：US4712127B1

公开(公告)日：1997-05-06

申请号：US55615983

申请日：1983-11-29

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： COLOMBO PIERO ,  CELLAI MARINO ,  MARTIIS DE COGNETTI CARLO

IPC: H01L23/48 ,  H01L23/28 ,  H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L23/12

CPC classification number: H01L23/4334 ,  H01L23/3121 ,  H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01014 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/00

公开(公告)号：US5428301A

公开(公告)日：1995-06-27

申请号：US12976693

申请日：1993-09-30

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： MCCLURE DAVID C

IPC: G11C11/408 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H03K19/003

CPC classification number: G11C29/787 ,  G11C29/84

公开(公告)号：US20030190781A1

公开(公告)日：2003-10-09

申请号：US10305437

申请日：2002-11-26

Applicant: SGS-Thomson Microelectronics, Inc.

Inventor： Robert Louis Hodges ,  Loi Ngoc Nguyen

IPC: H01L021/8234 ,  H01L021/3205 ,  H01L029/76

CPC classification number: H01L21/76897 ,  H01L21/768 ,  H01L27/105 ,  H01L29/6659

Abstract: An integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells.

Abstract translation: 一种集成电路存储器制造工艺和结构，其中在存储器芯片的外围（以及可选地在地线上）执行腐蚀，而不是存储在存储器单元的晶体管上。

公开(公告)号：US20030017666A1

公开(公告)日：2003-01-23

申请号：US10247177

申请日：2002-09-19

Applicant: SGS-Thomson Microelectronics S.r.l.

Inventor： Giuseppe Queirolo ,  Giovanni Ferroni

IPC: H01L021/8238

CPC classification number: H01L28/82 ,  C23C16/24 ,  H01L21/28273 ,  H01L21/28556 ,  H01L21/3205

Abstract: The electrical performance of a dielectric film for capacitive coupling in an integrated structure is enhanced by forming the polycrystalline electrically conductive layer coupled with the dielectric film substantially unigranular over the coupling area, commonly to be defined by patterning the stacked dielectric and conductive layers. The process forms a polycrystalline silicon film having exceptionally large grains of a size on the same order of magnitude as the dimensions of the patterned details. These exceptionally large grains are obtained by preventing the formation of nullprecursor nucleinull of subsequent grain formation and growth at the deposition interface with the dielectric that are apparently formed during the first instants of silicon CVD deposition and by successively growing the crystallites at a sufficiently low annealing temperature.

公开(公告)号：US20020140021A1

公开(公告)日：2002-10-03

申请号：US10158706

申请日：2002-05-30

Applicant: SGS-THOMSON MICROELECTRONICS S.R.L.

Inventor： Paolo Cappelletti

IPC: H01L029/76

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/49 ,  H01L29/495 ,  H01L29/513 ,  H01L29/518

Abstract: A non-volatile memory cell of the type which includes at least one floating gate transistor and which is realized over a semiconductor substrate includes a source region, and a drain region, separated by a channel region which is overlaid by a thin layer of gate oxide. The gate oxide isolates a floating gate region from the substrate. The floating gate region is coupled to a control gate terminal. The floating gate region of the memory cell develops a first potential barrier between the semiconductor substrate and the gate oxide layer, and a second different potential barrier between the floating gate region and the gate oxide.

Abstract translation: 包括至少一个浮置栅极晶体管并且在半导体衬底上实现的类型的非易失性存储单元包括源极区和漏极区，该沟道区由覆盖有栅极氧化物的薄层 。 栅极氧化物从衬底隔离浮栅区域。 浮栅区域耦合到控制栅极端子。 存储单元的浮置栅极区域在半导体衬底和栅极氧化物层之间形成第一势垒，并且在浮置栅极区域和栅极氧化物之间形成第二个不同的势垒。

公开(公告)号：US6434056B2

公开(公告)日：2002-08-13

申请号：US74647300

申请日：2000-12-21

Applicant: SGS THOMSON MICROELECTRONICS

Inventor： BRIGATI ALESSANDRO ,  DEVIN JEAN ,  LECONTE BRUNO

IPC: G11C16/02 ,  G06F12/06 ,  G11C7/00 ,  G11C8/12

CPC classification number: G11C8/12 ,  G11C7/00

Abstract: Two different types of memory are integrated on the same type of integrated circuit. A microcontroller is associated with each of these memories. In order that the independence of operation of these microcontrollers may be ensured, they are each provided with time delay circuits whose role is to maintain the read or write operation of one microcontroller when another is selected.

Abstract translation: 两种不同类型的存储器集成在相同类型的集成电路上。 微控制器与这些存储器中的每一个相关联。 为了确保这些微控制器的操作的独立性，它们各自被提供有时间延迟电路，其作用是在选择另一个微控制器时保持一个微控制器的读取或写入操作。